AM3359 Datasheet, PDF (150/162 Pages) Texas Instruments – AM335x ARM Cortex-A8 Microprocessors (MPUs)

AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
SPRS717 – OCTOBER 2011
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5.6.1.2.5 DDR2 Keepout Region
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2
keepout region is defined for this purpose and is shown in Figure 5-45. The size of this region varies with
the placement and DDR routing. Additional clearances required for the keepout region are shown in
Table 5-32.
A1
DDR2
Device
A1
Region should encompass all DDR2 circuitry and varies depending
on placement. Non-DDR2 signals should not be routed on the DDR
signal layers within the DDR2 keep out region. Non-DDR2 signals may
be routed in the region provided they are routed on layers separated
from DDR2 signal layers by a ground layer. No breaks should be
allowed in the reference ground layers in this region. In addition, the
1.8 V power plane should cover the entire keep out region.
Figure 5-45. DDR2 Keepout Region
5.6.1.2.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.
Table 5-33 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DDR2 interfaces and DDR2 device. Additional bulk
bypass capacitance may be needed for other circuitry.
Table 5-33. Bulk Bypass Capacitors
No. Parameter
1 DVDD18 bulk bypass capacitor count⁽¹⁾
Min
Max Unit
6
Devices
2 DVDD18 bulk bypass total capacitance
3 DDR#1 bulk bypass capacitor count⁽¹⁾
4 DDR#1 bulk bypass total capacitance⁽¹⁾
5 DDR#2 bulk bypass capacitor count⁽²⁾
6 DDR#2 bulk bypass total capacitance⁽¹⁾⁽²⁾
60
μF
1
Devices
10
μF
1
Devices
10
μF
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass capacitors. Use half of these capacitors for DDR[0] and half for DDR[1].
(2) Only used on 32-bit wide DDR2 memory systems.
5.6.1.2.7 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, MPU/DDR power, and
MPU/DDR ground connections. Table 5-34 contains the specification for the HS bypass capacitors as well
as for the power connections on the PCB.
150 Peripheral Information and Timings
Copyright © 2011, Texas Instruments Incorporated
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