TPS65217A Datasheet, PDF (15/86 Pages) Texas Instruments – SINGLE-CHIP PMIC FOR BATTERY-POWERED SYSTEMS

TPS65217A, TPS65217B, TPS65217C
www.ti.com
MODES OF OPERATION
SLVSB64E – NOVEMBER 2011 – REVISED JULY 2012
OFF
In OFF mode the PMIC is completely shut down with the exception of a few circuits to monitor the AC,
USB, and push-button input. All power rails are turned off and the registers are reset to their default
values. The I²C communication interface is turned off. This is the lowest-power mode of operation. To exit
OFF mode one of the following wake-up events has to occur:
• The push button input is pulled low.
• The USB supply is connected (positive edge).
• The AC adapter is connected (positive edge).
To enter OFF state, set the OFF bit in the STATUS register to ‘1’ and then pull the PWR_EN
pin low. Please note that in normal operation OFF state can only be entered from ACTIVE
state. Whenever a fault occurs during operation such as thermal shutdown, power-good fail,
under voltage lockout, or PWR_EN pin timeout, all power rails are shut-down and the device
goes to OFF state. The device will remain in OFF state until the fault has been removed and
a new power-up event has occurred.
ACTIVE This is the typical mode of operation when the system is up and running. All DCDC converters, LDOs,
load switches, WLED driver, and battery charger are operational and can be controlled through the I²C
interface.
After a wake-up event the PMIC enables all rails not controlled by the sequencer and pulls
the nWAKEUP pin low to signal the event to the host processor. The device will enter
ACTIVE state only if the host asserts the PWR_EN pin within 5 seconds after the wake-up
event. Otherwise it will enter OFF state. In ACTIVE state the sequencer is triggered to bring
up the remaining power rails. The nWAKEUP pin returns to HiZ mode after PWR_EN pin has
been asserted. A timing diagram is shown in Figure 2. ACTIVE state can also be entered
from SLEEP state directly by pulling the PWR_EN pin high. See SLEEP state description for
details.
To exit ACTIVE mode the PWR_EN pin needs to be pulled low.
SLEEP SLEEP state is a low-power mode of operation intended to support system standby. Typically all power
rails are turned off with the exception of LDO1 and the registers are reset to their default values. LDO1
remains operational but can support only limited amount of current (100 µA typical).
To enter SLEEP state, set the OFF bit in the STATUS register to ‘0’ (default) and then pull
the PWR_EN pin low. All power rails controlled by the power-down sequencer will be shut
down and after 1s the device enters SLEEP state. If LDO1 was enabled in ACTIVE state, it
will remain enabled in SLEEP sate. All rails not controlled by the power-down sequencer will
also maintain state. The battery charger will remain active for as long as either USB or AC
supply is connected to the device. Please note that all register values are reset as the device
enters in SLEEP state, including charger parameters.
The device enters ACTIVE state after it detects a wake-up event as described in the
sections above. In addition, the device transitions from SLEEP to ACTIVE state when the
PWR_EN pin is pulled high. This allows the system host to switch the PMIC between
ACTIVE to SLEEP state by control of the PWR_EN pin only.
RESET The TPS65217 can be reset by either pulling the nRESET pin low or holding the PB_IN pin low for more
than 8 seconds. All rails will be shut-down by the sequencer and all register values are reset to their
default values. Rails not controlled by the sequencer are shut down immediately. The device remains in
this state for as long as the reset pin is held low and the nRESET pin must be high to exit RESET state.
However, the device will remain in RESET state for a minimum of 1s before it returns to ACTIVE state. As
described in the ACTIVE section, the PWR_EN pin must be asserted within 5 seconds of nWAKEUP-pin-
low to enter ACTIVE state. Please note that the RESET function power-cycles the device and only shuts
down the output rails temporarily. Resetting the device does not lead to OFF state.
If the PB_IN pin is kept low for an extended amount of time, the device will continue to cycle
between ACTIVE and RESET state, entering RESET every 8 s.
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
15
Product Folder Link(s): TPS65217A TPS65217B TPS65217C