TPS3813J25_16 Datasheet, PDF (15/24 Pages) Texas Instruments – Family Processor Supervisory Circuits With Window-Watchdog

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TPS3813J25, TPS3813L30, TPS3813K33, TPS3813I50
SLVS331H – DECEMBER 2000 – REVISED JULY 2016
10 Power Supply Recommendations
These devices are designed to operate from an input supply with a voltage range from 2 V to 6 V. An input
supply capacitor is not required for this device; however, if the input supply is noisy, then good analog practice is
to place a 0.1-µF capacitor between the VDD pin and the GND pin. This device has a 7-V absolute maximum
rating on the VDD pin. If the voltage supply providing power to VDD is susceptible to any large voltage transient
that can exceed 7 V, additional precautions must be taken.
In applications where the WDI input may experience a negative voltage while V_DD is ramping from 0 V to 0.8 V,
the V_DD slew rate in this range must be greater than 10 V/s. A negative voltage on the WDI input along with a
slew rate less than 10 V/s could result in a greatly reduced watchdog window time and reset output delay time.
11 Layout
11.1 Layout Guidelines
Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic bypass capacitor near the VDD pin.
11.2 Layout Example
Pullup
Voltage
WDI
Signal
TPS3813
1
6
2
4
3
4
RESET
Flag
CVDD
Figure 10. TPS3813xxx Layout Example
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