TMS370CX9X_05 Datasheet, PDF (15/55 Pages) Texas Instruments – 8-BIT MICROCONTROLLER

TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B – JANUARY 1996 – REVISED FEBRUARY 1997
privileged operation and EEPROM write-protection override (continued)
The write-protect override (WPO) mode provides an external hardware method of overriding the
write-protection registers of data EEPROM on the TMS370Cx9x. Applying a 12-V input to the MC pin after the
RESET input goes high (logic 1) enters the WPO mode. The high voltage on MC during the WPO mode is not
the programming voltage for the data EEPROM or program EPROM. All EEPROM programming voltages are
generated on-chip. The WPO mode provides hardware system level capability to modify the content of the data
EEPROM while the device remains in the application, but only while requiring a 12-V external input on the MC
pin (normally not available in the end application except in a service or diagnostic environment).
low-power and IDLE modes
The TMS370Cx9x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For
mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the
time when the mask is manufactured.
The STANDBY and HALT low power modes significantly reduce power consumption by reducing or stopping
the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes
is entered by executing the idle instruction when the PWRDWN/IDLE bit in register SCCR2 has been set to one.
The HALT / STANDBY bit in SCCR2 controls which low-power mode is entered.
In the STANDBY mode (HALT/STANDBY = 0), all CPU activity and most peripheral module activity is stopped;
however, the oscillator, internal clocks, and timer 1 remain active. System processing is suspended until a
qualified interrupt (hardware RESET, external interrupt on INT1, or timer 1 interrupt) is detected.
In the HALT mode (HALT/STANDBY = 1), the TMS370Cx9x is placed in its lowest power-consumption mode.
The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is
suspended until a qualified interrupt (hardware RESET or an external interrupt on INT1) is detected. The
low-power mode selection bits are summarized in Table 9.
Table 9. Low-Power/Idle Control Bits
POWER-DOWN CONTROL BITS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{PWRDWN/IDLE HALT/STANDBY}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _(SCCR2.6)
(SCCR2.7)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ₁
1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 0
X
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{X = don’t care}
MODE SELECTED
STANDBY
HALT
IDLE
When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the
SCCR2.6–7 bits is ignored. In addition, if an IDLE instruction is executed when low-power modes are disabled
through a programmable contact, the device always enters the IDLE mode.
To provide a method of always exiting low-power modes for mask-ROM devices, INT1 is enabled automatically
as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This
means that the NMI is always generated, regardless of the interrupt enable flags.
The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),
CPU registers (stack pointer, program counter, and status register), I/O pin direction and output data, and status
registers of all on-chip peripheral functions. Since all CPU instruction processing is stopped during the
STANDBY and HALT modes, the clocking of the watchdog timer is inhibited.
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