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SN75DP122A Datasheet, PDF (15/37 Pages) Texas Instruments – DisplayPort 1:2 Switch With Integrated TMDS Translator
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SN75DP122A
www.ti.com............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
CIO(AUX)
PARAMETER
Input/output capacitance
AUX_I2C pins
VIH(AUX)
VIL(AUX)
VOL(AUX)
Ilkg(I2C)
High-level input voltage
Low-level input voltage
Low-level output voltage
Input leakage current
AUX_I2C pins
AUX_I2C pins
AUX_I2C pins
I2C SDA/SCL pins
CIO(I2C)
Input/output capacitance
I2C SDA/SCL pins
VIH(I2C)
VIL(I2C)
VOL(I2C)
High-level input voltage
Low-level input voltage
Low-level output voltage
I2C SDA/SCL pins
I2C SDA/SCL pins
I2C SDA/SCL pins
TEST CONDITIONS
DC bias = 1 V, AC = 1.4 Vp-p,
f = 100 kHz
IO = 4 mA
VCC = 3.6 V, VI = 4.95V
DC bias = 2.5 V,
AC = 3.5 Vp-p, f = 100 kHz
IO = 4 mA
MIN TYP MAX
15
1.6
–0.2
0.4
0.5
0.6
–10
10
15
2.1
-0.2
1.5
0.2
UNIT
pF
V
V
V
µA
pF
V
V
V
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
tPLH1
tPHL1
tPLH2
tPHL2
tf1
tf2
fSCL
tW(L)
tW(H)
tSU1
th(1)
T(buf)
tsu(2)
th(2)
tsu(3)
PARAMETER
Propagation delay time, low to high
Propagation delay time, high to low
Propagation delay time, low to high
Propagation delay time, high to low
Output signal fall time
Output signal fall time
SCL clock frequency for internal register
Clock LOW period for I2C register
Clock HIGH period for internal register
Internal register setup time, SDA to SCL
Internal register hold time, SCL to SDA
Internal register bus free time between STOP and START
Internal register setup time, SCL to START
Internal register hold time, START to SCL
Internal register hold time, SCL to STOP
TEST CONDITIONS
Source to sink
Source to sink
Sink to source
Sink to source
Sink side
Source side
Source side
Source side
Source side
Source side
Source side
Source side
Source side
Source side
Source side
MIN TYP MAX UNIT
204
459 ns
35
140 ns
80
251 ns
35
200 ns
20
72 ns
20
72 ns
100 kHz
4.7
µs
4.0
µs
250
ns
0
µs
4.7
µs
4.7
µs
4.0
µs
4.0
µs
VCC
3.3 V
PULSE
GENERATOR
D.U.T.
RT
VIN
VOUT
RL = 2 kW
CL = 100 pF
Figure 14. Source Side Test Circuit (AUX_I2C)
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP122A
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