PCM3168A Datasheet, PDF (15/66 Pages) Texas Instruments – 24-Bit, 96-kHz/192-kHz, 6-In/8-Out Audio Codec with Differential Input/Output

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PCM3168A
SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016
8.13 Timing Requirements: Four-Wire Serial Control Interface⁽¹⁾
Refer to Figure 8.
MIN
MAX
UNIT
t_MCY
t_MCL
t_MCH
t_MHH
t_MSS
t_MSH
t_MDH
t_MDS
t_MDD
t_MDR
MC pulse cycle time
MC low-level time
MC high-level time
MS high-level time
MS falling edge to MC rising edge
MS rising edge from MC rising edge for LSB
MDI hold time
MDI setup time
MDO enable or delay time from MC falling edge
MDO disable time from MS rising edge
100
ns
40
ns
40
ns
t_MCY
ns
30
ns
15
ns
15
ns
15
ns
0
30
ns
0
30
ns
(1) These timing parameters are critical for proper control port operation.
8.14 Timing Requirements: SCL and SDA Control Interface
Refer to Figure 9.
f_SCL
t_BUF
t_LOW
t_HI
t_S-SU
t_S-HD
t_D-SU
t_D-HD
SCL clock frequency
Bus free time between STOP and START condition
Low period of the SCL clock
High period of the SCL clock
Setup time for START/Repeated START condition
Hold time for START/Repeated START condition
Data setup time
Data hold time
STANDARD MODE
MIN
MAX
100
4.7
4.7
4.0
4.7
4.0
250
0
3450
t_SCL-R
Rise time of SCL signal
1000
t_SCL-F
Fall time of SCL signal
1000
t_SDA-R
Rise time of SDA signal
1000
t_SDA-F
t_P-SU
t_GW
C_B
V_NH
V_NL
V_HYS
Fall time of SDA signal
Setup time for STOP condition
Allowable glitch width
Capacitive load for SDA and SCL line
Noise margin at high level for each connected device
(including hysteresis)
Noise margin at low level for each connected device
(including hysteresis)
Hysteresis of Schmitt-trigger input
4.0
0.2 × V_DD
0.1 × V_DD
N/A
1000
N/A
400
FAST MODE
MIN
MAX
400
1.3
1.3
0.6
0.6
0.6
100
0
900
20 + (0.1 ×
C_B)
300
20 + (0.1 ×
C_B)
300
20 + (0.1 ×
C_B)
300
20 + (0.1 ×
C_B)
300
0.6
50
100
0.2 × V_DD
0.1 × V_DD
0.05 × V_DD
UNIT
kHz
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
μs
pF
V
V
V
High
System Clock
(SCKI)
Low
t_SCH
t_SCL
t_SCY
Figure 1. System Clock Timing Requirements
2.0 V
0.8 V
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