PCA9554_15 Datasheet, PDF (15/34 Pages) Texas Instruments – SMBus I/O Expander With Interrupt Output

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PCA9554
SCPS128C – JULY 2006 – REVISED JUNE 2014
Device Functional Modes (continued)
8.2.3 Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, t_iv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting, data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal.
Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of
the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an
interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin
does not match the contents of the Input Port register. Because each 8-pin port is read independently, the
interrupt caused by port 0 is not cleared by a read of port 1 or vice versa.
The INT output has an open-drain structure and requires pullup resistor to V_CC.
8.2.3.1 Interrupt Errata
Description
The INT will be improperly de-asserted if the following two conditions occur:
1. The last I²C command byte (register pointer) written to the device was 00h.
NOTE
This generally means the last operation with the device was a Read of the input
register. However, the command byte may have been written with 00h without ever
going on to read the input register. After reading from the device, if no other command
byte written, it will remain 00h.
2. Any other slave device on the I²C bus acknowledges an address byte with the R/W bit set high
System Impact
Can cause improper interrupt handling as the Master will see the interrupt as being cleared.
System Workaround
Minor software change: User must change command byte to something besides 00h after a Read operation to
the PCA9554 device or before reading from another slave device.
NOTE
Software change will be compatible with other versions (competition and TI redesigns) of
this device.
8.3 Programming
8.3.1 I²C Interface
The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I²C communication with this device is initiated by a master sending a start condition, a high-to-low transition on
the SDA input/output while the SCL input is high (see Figure 19). After the start condition, the device address
byte is sent, MSB first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must
not be changed between the start and the stop conditions.
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