OPA3690_14 Datasheet, PDF (15/39 Pages) Texas Instruments – Triple, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER

OPA3690
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Again, an additional resistor (50Ω in this case) is
included directly in series with the noninverting input.
This minimum recommended value provides part of
the dc source resistance matching for the
noninverting input bias current. It is also used to form
a simple parasitic pole to roll off the frequency
response at very high frequencies ( > 500MHz) using
the input parasitic capacitance to form a bandlimiting
pole. The gain resistor (R_G) is ac-coupled, giving the
circuit a dc gain of +1, which puts the input dc bias
voltage (2.5V) on the output as well. The output
voltage can swing to within 1V of either supply pin
while delivering > 100mA output current. A
demanding 100Ω load to a midpoint bias is used in
this characterization circuit. The new output stage
circuit used in the OPA3690 can deliver large bipolar
output currents into this midpoint load with minimal
crossover distortion, as shown in the ±5V supply
harmonic distortion plots.
SINGLE-SUPPLY ADC INTERFACE
Most modern, high-performance ADCs (such as the
TI ADS8xx and ADS9xx series from Texas
Instruments) operate on a single +5V (or lower)
power supply. It has been a considerable challenge
for single-supply op amps to deliver a low distortion
input signal at the ADC input for signal frequencies
exceeding 5MHz. The high slew rate, exceptional
output swing, and high linearity of the OPA3690
make it an ideal single-supply ADC driver. The circuit
on the front page shows one possible interface
particularly suited to differential I/O, ac-coupled
requirements. Figure 39 shows the test circuit of
Figure 37 modified for a capacitive (ADC) load and
with an optional output pull-down resistor (R_B). This
circuit would be suitable to dual-channel ADC driving
with a single-ended I/O.
SBOS237G – MARCH 2002 – REVISED MARCH 2010
The OPA3690 in the circuit of Figure 39 provides
> 200MHz bandwidth for a 2V_PP output swing.
Minimal 3rd-harmonic distortion or two-tone,
3rd-order intermodulation distortion will be observed
due to the very low crossover distortion in the
OPA3690 output stage. The limit of output
Spurious-Free Dynamic Range (SFDR) will be set by
the 2nd-harmonic distortion. Without R_B, the circuit of
Figure 39 measured at 10MHz shows an SFDR of
57dBc. This may be improved by pulling additional dc
bias current (I_B) out of the output stage through the
optional R_B resistor to ground (the output midpoint is
at 2.5V for Figure 39). Adjusting I_B gives the
improvement in SFDR shown in Figure 38. SFDR
improvement is achieved for I_B values up to 5mA,
with worse performance for higher values. Using the
dual OPA3690 in an I/Q receiver channel will give
matched ac performance through high frequencies.
70
68 ^{VO = 2VPP, 10MHz}
66
64
62
60
58
56
54
52
50
0 123 456 78
Output Pull-Down Current (mA)
9 10
Figure 38. SFDR vs I_B
+5V
V_I
1V_PP
0.1mF
698W
50W
59W
698W
Power- supply decoupling not shown.
1/3
OPA3690
402W
R_S
30W
50pF
2.5V DC
±1V AC
ADC Input
402W
0.1mF
R_B
I_B
Figure 39. Single-Supply ADC Input Driver (one of three channels)
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA3690
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