LP2983 Datasheet, PDF (15/25 Pages) National Semiconductor (TI) – Micropower 150 mA Voltage Regulator in SOT-23 Package For Output Voltages 1.2V Designed for Use with Very Low ESR Output Capacitors

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LP2983
SNVS170D – OCTOBER 2001 – REVISED APRIL 2016
8.2.2.2 Capacitor Characteristics
The LP2983 was designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer: for capacitance values in the 2.2-µF to 4.7-µF range, ceramics are the least expensive and also have the
lowest ESR values (which makes them best for eliminating high-frequency noise).
One disadvantage of ceramic capacitors is that their capacitance can vary with temperature. Most large value
ceramic capacitors (≥ 2.2 µF) are manufactured with the Z5U or Y5V temperature characteristic, which results in
the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C.
This could cause problems if a 2.2-µF capacitor were used on the output since it will drop down to approximately
1 µF at high ambient temperatures (which could cause the LP2983 to oscillate). If Z5U or Y5V capacitors are
used on the output, a minimum capacitance value of 4.7 µF must be observed.
A better choice for temperature coefficient in ceramic capacitors is X7R, which holds the capacitance within
±15%. Unfortunately, the larger values of capacitance are not offered by all manufacturers in the X7R dielectric.
8.2.2.3 Power Dissipation
Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is
critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and
load conditions and can be calculated with Equation 1.
P_D(MAX) = (V_IN(MAX) – V_OUT) × I_OUT
(1)
Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available
voltage drop option that would still be greater than the dropout voltage (V_DO). However, keep in mind that higher
voltage drops result in better dynamic (that is, PSRR and transient) performance.
On the SOT-23 (DBV) package, the primary conduction path for heat is through the pins to the PCB. The
maximum allowable junction temperature (T_J(MAX))determines maximum power dissipation allowed (P_D(MAX)) for
the device package.
Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance
(R_θJA) of the combined PCB and device package and the temperature of the ambient air (T_A), according to
Equation 2 or Equation 3:
T_J(MAX) = T_A(MAX) + (R_θJA × P_D(MAX))
(2)
P_D = T_J(MAX) – T_A(MAX) / R_θJA
(3)
Unfortunately, this R_θJA is highly dependent on the heat-spreading capability of the particular PCB design, and
therefore varies according to the total copper area, copper weight, and location of the planes. The R_θJA recorded
in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper-
spreading area, and is to be used only as a relative measure of package thermal performance. For a well-
designed thermal layout, R_θJA is actually the sum of the package junction-to-case (bottom) thermal resistance
(R_θJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink.
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