LMK04906_14 Datasheet, PDF (15/71 Pages) Texas Instruments – Low-Noise Clock Jitter Cleaner with Dual Loop PLLs

LMK04906 EVALUATION BOARD OPERATING INSTRUCTIONS
Connector Name
Signal Type,
Input/Output
Description
Reference Clock Inputs for PLL1 (CLKin0, 1, 2).
CLKin1 can alternatively be used as an External
Feedback Clock Input (FBCLKin) in 0-delay mode or
an RF Input (Fin) in External VCO mode.
Reference Clock Inputs for PLL1 (CLKin0, 1)
FBCLKin/CLKin1* is configured by default for a
single-ended reference clock input from a 50-ohm
source. The non-driven input pin (FBCLKin/CLKin1)
is connected to GND with a 0.1 uF. CLKin0/CLKin0*
is configured by default for a differential reference
clock input from a 50-ohm source.
Populated:
CLKin0, CLKin0*,
FBCLKin*/CLKin1*
CLKin2, CLKin2*
Not Populated:
FBCLKin/CLKin1
Analog,
Input
CLKin1* is the default reference clock input selected in
CodeLoader. The clock input selection mode can be
programmed on the Bits/Pins tab via the
CLKin_Select_MODE control. Refer to the
LMK04906 Family Datasheet section “Input Clock
Switching” for more information.
AC coupled Input Clock Swing Levels
Input
Mode Min Max
Differential Bipolar or 0.5 3.1
Single Ended CMOS 0.25 2.4
Units
Vpp
Vpp
External Feedback Input (FBCLKin) for 0-Delay
CLKin1 is shared for use with FBCLKin as an external
feedback clock input to PLL1 for 0-delay mode. See
section, Programming 0-Delay Mode in CodeLoader
below, for more details on using 0-delay mode with the
evaluation board and the evaluation board software.
RF Input (Fin) for External VCO
CLKin1 is also shared for use with Fin as an RF input
for external VCO mode using the onboard VCO
footprint (U3) or add-on VCO board. To enable Dual
PLL mode with External VCO, the following registers
must be properly configured in CodeLoader:
MODE = (3) Dual PLL, Ext VCO (Fin), (5)
Dual PLL, Ext VCO, 0-Delay, (11) PLL2, Ext
VCO (Fin)
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