LM3S1601_16 Datasheet, PDF (15/592 Pages) Texas Instruments – Stellaris LM3S1601 Microcontroller

Stellaris^® LM3S1601 Microcontroller
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Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 110
Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 110
Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 112
CPU ID Base (CPUID), offset 0xD00 ............................................................................... 113
Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 114
Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 117
Application Interrupt and Reset Control (APINT), offset 0xD0C ......................................... 118
System Control (SYSCTRL), offset 0xD10 ....................................................................... 120
Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 122
System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 124
System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 125
System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 126
System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 127
Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 131
Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 137
Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 138
Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 139
MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 140
MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 141
MPU Region Number (MPUNUMBER), offset 0xD98 ....................................................... 143
MPU Region Base Address (MPUBASE), offset 0xD9C ................................................... 144
MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 ....................................... 144
MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC ...................................... 144
MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 ....................................... 144
MPU Region Attribute and Size (MPUATTR), offset 0xDA0 ............................................... 146
MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 .................................. 146
MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 .................................. 146
MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 .................................. 146
System Control ............................................................................................................................ 162
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 177
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 ........................................................ 179
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 180
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 181
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 182
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 183
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 184
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 185
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 188
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 189
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 191
Register 12: Device Identification 1 (DID1), offset 0x004 ..................................................................... 192
Register 13: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 194
Register 14: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 195
Register 15: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 197
Register 16: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 199
Register 17: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 201
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 203
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 204
July 16, 2014
15
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