LM3495_14 Datasheet, PDF (15/35 Pages) Texas Instruments – Emulated Peak Current Mode Buck Controller for Low Output Voltage

LM3495
www.ti.com
SNVS410E – FEBRUARY 2006 – REVISED NOVEMBER 2007
Care must be taken to prevent errant pulses from triggering the synchronization circuitry. In applications that will
not synchronize to an external clock, C_SYNC should be connected from the FREQ/SYNC pin to signal ground as a
noise filter. When a clock pulse is first detected, the LM3495 begins switching at the external clock frequency.
Noise or a short burst of clock pulses can result in off times as long as 7.5 µs for the high-side FET if they occur
while the internal synchronization circuits are adjusting.
LM3495
FREQ/SYNC
C_SYNC
100 pF
R_FRQ
External
Clock
Figure 5. Clock Synchronization Circuit
MOSFET GATE DRIVE
The LM3495 has two gate drivers designed for driving N-channel MOSFETs in a synchronous mode. Power for
the high-side driver is supplied through the BOOST pin. For the high-side gate drive to fully turn on the top FET,
the BOOST pin voltage must be at least one threshold voltage, V_GS(th), greater than V_IN. This voltage is supplied
from a local charge pump structure which consists of a Schottky diode and 0.1 µF capacitor, shown in Figure 6.
Both the bootstrap and the low-side FET driver are fed from VLIN5, which is the output of a 4.7V internal linear
regulator. This regulator has a dropout voltage of approximately 1V. If V_IN drops below 4V, an internal switch
shorts the VIN and VLIN5 pins together. The drive voltage for the top FET driver is therefore VLIN5-V_D, where V_D
is the drop across the Schottky diode D1. This information is needed to select the type of MOSFETs to be used.
D1
VLIN5
BOOST
C_BOOT
V_IN
HG
LM3495
SW/CSH
LG
Q1
L1
Q2
+ _Co
Figure 6. Bootstrap Circuit
INPUT VOLTAGE BELOW 5.5V
The LM3495 includes an internal 4.7V linear regulator connected from the VIN pin to the VLIN5 pin. This linear
regulator feeds the logic and FET drive circuitry. For input voltages less than 5.5V, the VIN and VLIN5 pins can
be shorted together externally. The external short circuit bypasses both the internal linear regulator and the
internal PMOS switch, allowing the full input voltage to be used for driving the power FETs and minimizing
conduction loss in the LM3495 itself. For voltage inputs that range above and below 5.5V the LM3495 must not
use a short from VIN to VLIN5.
UNDER VOLTAGE LOCK-OUT
The 2.6V turn-on threshold on the voltage at VIN has a built in hysteresis of 300 mV. If input voltage drops below
2.3V the chip enters under voltage lock-out (UVLO) mode. UVLO consists of turning off both the top and bottom
FETs and remaining in that condition until input voltage rises above 2.6V.
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