DS90CP04_15 Datasheet, PDF (15/24 Pages) Texas Instruments – 1.5 Gbps 4x4 LVDS Crosspoint Switch

DS90CP04
www.ti.com
SNLS154I – JANUARY 2002 – REVISED APRIL 2013
Switch Expansion For Minimum Programming Latency
Programming data ripples through the array through RSO and RSCLK in the row and CSO and CSCLK in the
first column. LOAD pins of all devices are electrically tied together and driven by the same “load” signal. To
prevent excessive stub length in the array from affecting the signal quality of LOAD, it is recommended that the
load signal is distributed to each row or column in large crosspoint array applications.
NUMBER OF SCLK POSITIVE EDGE TRANSITIONS
0
30
60
DEVICE 0
CONTROL WORD 1
[01 F] [1][0] [1][1][1][1]
CONTROL WORD 1
[01 F] [0][0] [2][2][4][4]
DEVICE 1
(+7 Clocks)
[01 F] [0][0] [1][1][1][1]
[01 F] [3F][0] [2][2][4][4]
Device 1
Configuration Ready to
Load
Device 0
Configuration Ready
to Load
Programming Example
CONFIGURATION WRITE
30 Bit Control Word: [WRITE FRAME] [ROW ADDRESS][COLUMN ADDRESS] [OUT1][OUT2][OUT3][OUT4]
ARRAY WRITE
[01 1111] [0][1] [1][1][1][1] //*Array position 1, Broadcast IN1 *//
[01 1111] [0][0] [2][2][4][4] //*Array position 0, Connect IN2 to OUT1 and 2, IN4 to OUT3 and OUT4 *//
LOAD = H and SCLK = LH
NUMBER OF SCLK POSITIVE EDGE TRANSITIONS
0
30
60
90
120
150
DEVICE 0
CONTROL WORD 1 CONTROL WORD 2 CONTROL WORD 3 CONTROL WORD 4
[01 F] [0][3] [4][4][4][4] [01 F] [0][2] [0][3][0][0] [01 F] [0][1] [0][0][2][0] [01 F] [0][0] [1][2][3][4]
DEVICE 1
(+7 Clocks)
DEVICE 2
(+14 Clocks)
[01 F] [0][2] [4][4][4][4] [01 F] [0][1] [0][3][0][0] [01 F] [0][0] [0][0][2][0] [01 F] [0][3F] [1][2][3][4]
[01 F] [0][1] [4][4][4][4] [01 F] [0][0] [0][3][0][0] [01 F] [0][3F] [0][0][2][0] [01 F] [0][3E] [1][2][3][4]
DEVICE 3
(+21 Clocks)
[01 F] [0][0] [4][4][4][4] [01 F] [0][3F] [0][3][0][0] [01 F] [0][3E] [0][0][2][0] [01 F] [0][3D] [1][2][3][4]
Device 3
Configuration
Ready to Load
Device 2
Configuration
Ready to Load
Device 1
Configuration
Ready to Load
Device 0
Configuration
Ready to Load
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