CC2543_16 Datasheet, PDF (15/30 Pages) Texas Instruments – System-on-Chip for 2.4-GHz RF Applications

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CC2543
SWRS107E – APRIL 2012 – REVISED OCTOBER 2013
BLOCK DIAGRAM
A block diagram of the CC2543 is shown in Figure 7. The modules can be roughly divided into one of three
categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given. See CC2543/44/45 User's
Guide (SWRU283) for more details.
RESET_N
XOSC_Q2
XOSC_Q1
RESET
32-MHz
CRYSTAL OSC
WATCHDOG
TIMER
CLOCK MUX
and
CALIBRATION
DEBUG
INTERFACE
HIGH-
SPEED
RC-OSC
32-kHz
RC-OSC
POWER ON RESET
BROWN OUT
ON-CHIP VOLTAGE
REGULATOR
VDD (2 V–3.6 V)
DCOUPL
SLEEP TIMER
POWER MANAGEMENT CONTROLLER
P2_2
P2_1
P2_0
P1_4
P1_3
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
8051 CPU
CORE
PDATA
XRAM
IRAM
SFR
MEMORY
ARBITRATOR
DMA
UNIFIED
IRQ CTRL
ANALOG COMPARATOR
PSEUDO
RANDOM
NUMBER
GENERATOR
ΔΣ
ADC
AUDIO/DC
AES
ENCRYPTION
AND
DECRYPTION
RAM
SRAM
FLASH
FLASH
FIFOCTRL
FLASH CTRL
SRAM
ROM
RADIO REGISTERS
Link Layer Engine
SDA
SCL
USART 0
DEMODULATOR
MODULATOR
I²C
RECEIVE
TRANSMIT
TIMER 1 (16-Bit)
TIMER 2
(RADIO TIMER)
TIMER 3 (8-Bit)
TIMER 4 (8-Bit)
Figure 7. CC2543 Block Diagram
DIGITAL
ANALOG
MIXED
RF_P RF_N
B0301-12
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