BUF12840_14 Datasheet, PDF (15/32 Pages) Texas Instruments – Programmable Gamma-Voltage Generator with Integrated Two-Bank Memory and External EEPROM

BUF12840
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TIMING DIAGRAMS
Figure 16 describes the timing operations on the
BUF12840. Parameters for Figure 16 are defined in
Table 6. Bus definitions are:
Bus Idle: Both SDA and SCL lines remain high.
Start Data Transfer: A change in the state of the
SDA line, from high to low, while the SCL line is high,
defines a START condition. Each data transfer is
initiated with a START condition, denoted as S in
Figure 16.
Stop Data Transfer: A change in the state of the
SDA line from low to high while the SCL line is high
defines a STOP condition. Each data transfer
terminates with a repeated START or STOP
condition, denoted as P in Figure 16.
SBOS519A – OCTOBER 2010 – REVISED JULY 2011
Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not
limited and is determined by the master device. The
receiver acknowledges data transfer.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an Acknowledge
bit. A device that acknowledges must pull down the
SDA line during the Acknowledge clock pulse in such
a way that the SDA line is stable low during the high
period of the Acknowledge clock pulse. Setup and
hold times must be taken into account. On a master
receive, data transfer termination can be signaled by
the master generating a Not-Acknowledge on the last
byte that has been transmitted by the slave.
t_(LOW)
t_R
t_F
t_(HDSTA)
SCL
SDA
t_(BUF)
P
S
t_(HDSTA)
t_(HDDAT)
t_(HIGH)
t_(SUSTA)
t_(SUDAT)
S
t_(SUSTO)
P
Figure 16. Two-Wire Timing Diagram
Table 6. Timing Characteristics for Figure 16
PARAMETER
SCL operating frequency
Bus free time between
STOP and START condition
Hold time after repeated
START condition. After this
period, the first clock is
generated.
Repeated START condition
setup time
STOP condition setup time
Data hold time
Data setup time
SCL clock low period
SCL clock high period
Clock/data fall time
Clock/data rise time
for SCLK ≤ 100kHz
f_(SCL)
t_(BUF)
t_(HDSTA)
t_(SUSTA)
t_(SUSTO)
t_(HDDAT)
t_(SUDAT)
t_(low)
t_(high)
t_F
t_R
STANDARD MODE
MIN
MAX
0
0.1
4000
100
100
100
1 ⁽¹⁾
250
4700
4000
300
300
1000
FAST MODE
MIN
MAX
0
0.4
600
100
100
100
0 ⁽¹⁾
100
1300
600
300
300
1000
HIGH-SPEED MODE
MIN
MAX
0
3.4
160
UNITS
MHz
ns
100
ns
100
ns
100
ns
0 ⁽²⁾
ns
10
ns
160
ns
60
ns
160
ns
160
ns
ns
(1) For cases with a fall time of SCL less than 20ns and/or the rise time or fall time of SDA less than 20ns, the hold time should be greater
than 20ns.
(2) For cases with a fall time of SCL less than 10ns and/or the rise or fall time of SDA less than 10ns, the hold time should be greater than
10ns.
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