BQ27510-G3 Datasheet, PDF (15/30 Pages) Texas Instruments – System-Side Impedance Track Fuel Gauge With Direct Battery Connection

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bq27510-G3
SLUSAT1A – MARCH 2013 – REVISED NOVEMBER 2015
The “quick read” returns data at the address indicated by the address pointer. The address pointer, a register
internal to the I²C communication engine, increments whenever data is acknowledged by the fuel gauge or the
I²C master. “Quick writes” function in the same manner and are a convenient means of sending multiple bytes to
consecutive command locations (such as two-byte commands that require two bytes of data)
The following command sequences are not supported:
Attempt to write a read-only address (NACK after data sent by master):
Figure 8. Invalid Write
Attempt to read an address above 0x6B (NACK command):
Figure 9. Invalid Read
7.5.2.2 I²C Time Out
The I²C engine releases both SDA and SCL if the I²C bus is held low for 2 seconds. If the fuel gauge was
holding the lines, releasing them frees them for the master to drive the lines. If an external condition is holding
either of the lines low, the I²C engine enters the low-power sleep mode.
7.5.2.3 I²C Command Waiting Time
To ensure proper operation at 400 kHz, a t_(BUF) ≥ 66 μs bus free waiting time must be inserted between all
packets addressed to the fuel gauge. In addition, if the SCL clock frequency (f_SCL) is > 100 kHz, use individual 1-
byte write commands for proper data flow control. The following diagram shows the standard waiting time
required between issuing the control subcommand the reading the status result. For read-write standard
command, a minimum of 2 seconds is required to get the result updated. For read-only standard commands,
there is no waiting time required, but the host should not issue all standard commands more than two times per
second. Otherwise, the fuel gauge could result in a reset issue due to the expiration of the watchdog timer.
S ADDR [6:0] 0 A CMD [7:0] A DATA [7:0] A P 66ms
S ADDR [6:0] 0 A CMD [7:0] A DATA [7:0] A P 66ms
S ADDR [6:0] 0 A CMD [7:0] A Sr ADDR [6:0] 1 A DATA [7:0] A DATA [7:0]
Waiting time inserted between two 1-byte write packets for a subcommand and reading results
(required for 100 kHz < f_SCL £ 400 kHz)
NP
66ms
S ADDR [6:0] 0 A CMD [7:0] A DATA [7:0] A DATA [7:0] A P 66ms
S ADDR [6:0] 0 A CMD [7:0] A Sr ADDR [6:0] 1 A DATA [7:0] A DATA [7:0] N P
Waiting time inserted between incremental 2-byte write packet for a subcommand and reading results
(acceptable for f_SCL £ 100 kHz)
66ms
S ADDR [6:0] 0 A CMD [7:0] A Sr ADDR [6:0] 1 A DATA [7:0] A DATA [7:0] A
DATA [7:0] A DATA [7:0] N P 66ms
Waiting time inserted after incremental read
Figure 10. Standard I²C Command Waiting Time Required
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