ADC128S052CIMT Datasheet, PDF (15/25 Pages) Texas Instruments – 8-Channel, 200 kSPS to 500 kSPS, 12-Bit A/D Converter

ADC128S052
www.ti.com
SNAS333D – AUGUST 2005 – REVISED MARCH 2013
During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13
SCLK cycles the conversion is accomplished and the data is clocked out. SCLK falling edges 1 through 4 clock
out leading zeros while falling edges 5 through 16 clock out the conversion result, MSB first. If there is more than
one conversion in a frame (continuous conversion mode), the ADC will re-enter the track mode on the falling
edge of SCLK after the N*16th rising edge of SCLK and re-enter the hold/convert mode on the N*16+4th falling
edge of SCLK. "N" is an integer value.
The ADC128S052 enters track mode under three different conditions. In Figure 1, CS goes low with SCLK high
and the ADC enters track mode on the first falling edge of SCLK. In the second condition, CS goes low with
SCLK low. Under this condition, the ADC automatically enters track mode and the falling edge of CS is seen as
the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC enters
track mode. While there is no timing restriction with respect to the rising edges of CS and SCLK, see Figure 3 for
setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK.
While a conversion is in progress, the address of the next input for conversion is clocked into a control register
through the DIN pin on the first 8 rising edges of SCLK after the fall of CS. See Table 1, Table 2, Table 3.
There is no need to incorporate a power-up delay or dummy conversion as the ADC128S052 is able to acquire
the input signal to full resolution in the first conversion immediately following power-up. The first conversion result
after power-up will be that of IN0.
Bit 7 (MSB)
DONTC
Bit 6
DONTC
Bit 5
ADD2
Table 1. Control Register Bits
Bit 4
ADD1
Bit 3
ADD0
Bit 2
DONTC
Bit 1
DONTC
Bit 0
DONTC
Bit #:
7, 6, 2, 1, 0
5
4
3
Table 2. Control Register Bit Descriptions
Symbol:
DONTC
ADD2
ADD1
ADD0
Description
Don't care. The values of these bits do not affect the device.
These three bits determine which input channel will be sampled and
converted at the next conversion cycle. The mapping between codes and
channels is shown in Table 3.
ADD2
0
0
0
0
1
1
1
1
Table 3. Input Channel Selection
ADD1
0
0
1
1
0
0
1
1
ADD0
0
1
0
1
0
1
0
1
Input Channel
IN0 (Default)
IN1
IN2
IN3
IN4
IN5
IN6
IN7
ADC128S052 TRANSFER FUNCTION
The output format of the ADC128S052 is straight binary. Code transitions occur midway between successive
integer LSB values. The LSB width for the ADC128S052 is V_A / 4096. The ideal transfer characteristic is shown
in Figure 36. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB,
or a voltage of V_A / 8192. Other code transitions occur at steps of one LSB.
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