ADC121C021_14 Datasheet, PDF (15/44 Pages) Texas Instruments – I2C-Compatible, 12-Bit Analog-to-Digital Converter with Alert Function

ADC121C021, ADC121C021Q, ADC121C027
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Functional Description
SNAS415F – JANUARY 2008 – REVISED MARCH 2013
The ADC121C021 is a successive-approximation analog-to-digital converter designed around a charge-
redistribution digital-to-analog converter. Unless otherwise stated, references to the ADC121C021 in this section
will apply to both the ADC121C021 and the ADC121C027.
CONVERTER OPERATION
Simplified schematics of the ADC121C021 in both track and hold operation are shown in Figure 20 and
Figure 21 respectively. In Figure 20, the ADC121C021 is in track mode. SW1 connects the sampling capacitor to
the analog input channel, and SW2 equalizes the comparator inputs. The ADC is in this state for approximately
0.4µs at the beginning of every conversion cycle, which begins at the ACK fall of SDA. Conversions occur when
the conversion result register is read and when the ADC is in automatic conversion mode (see Automatic
Conversion Mode).
Figure 21 shows the ADC121C021 in hold mode. SW1 connects the sampling capacitor to ground and SW2
unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract
fixed amounts of charge to or from the sampling capacitor until the comparator is balanced. At this time the
digital word supplied to the DAC is also the digital representation of the analog input voltage. This digital word is
stored in the conversion result register and read via the 2-wire interface.
In the Normal (non-Automatic) Conversion mode, a new conversion is started after the previous conversion result
is read. In the Automatic Mode, conversions are started at set intervals, as determined by bits D7 through D5 of
the Configuration Register. The intent of the Automatic mode is to provide a "watchdog" function to ensure that
the input voltage remains within the limits set in the Alert Limit Registers. The minimum and maximum
conversion results can then be read from the Lowest Conversion Register and the Highest Conversion Register,
as described in Internal Registers.
V_IN
SW1
SAMPLING
CAPACITOR
SW2
CHARGE
REDISTRIBUTION
DAC
+
CONTROL
-
LOGIC
AGND
V_A/2
Figure 20. ADC121C021 in Track Mode
V_IN
SW1
SAMPLING
CAPACITOR
CHARGE
REDISTRIBUTION
DAC
+
-
SW2
CONTROL
LOGIC
AGND
V_A/2
Figure 21. ADC121C021 in Hold Mode
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