ADC08100_14 Datasheet, PDF (15/28 Pages) Texas Instruments – ADC08100 8-Bit, 20 Msps to 100 Msps, 1.3 mW/Msps A/D Converter

ADC08100
www.ti.com
SNAS060I – JUNE 2000 – REVISED MAY 2013
FUNCTIONAL DESCRIPTION
The ADC08100 uses a new, unique architecture that achieves over 7 effective bits at input frequencies up to and
beyond 50 MHz.
The analog input signal that is within the voltage range set by V_RT and V_RB is digitized to eight bits. Input voltages
below V_RB will cause the output word to consist of all zeroes. Input voltages above V_RB will cause the output
word to consist of all ones.
Incorporating a switched capacitor bandgap, the ADC08100 exhibits a power consumption that is proportional to
frequency, limiting power consumption to what is needed at the clock rate that is used. This and its excellent
performance over a wide range of clock frequencies makes it an ideal choice as a single ADC for many 8-bit
needs.
Data is acquired at the falling edge of the clock and the digital equivalent of that data is available at the digital
outputs 2.5 clock cycles plus t_OD later. The ADC08100 will convert as long as the clock signal is present. The
output coding is straight binary.
The device is in the active state when the Power Down pin (PD) is low. When the PD pin is high, the device is in
the power down mode, where the output pins hold the last conversion before the PD pin went high and the
device consumes just 1 mW.
Applications Information
REFERENCE INPUTS
The reference inputs V_RT and V_RB are the top and bottom of the reference ladder, respectively. Input signals
between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should
be within the range specified in Operating Ratings. Any device used to drive the reference pins should be able to
source sufficient current into the V_RT pin and sink sufficient current from the V_RB pin.
The reference bias circuit of Figure 30 is very simple and the performance is adequate for many applications.
However, circuit tolerances will lead to a wide reference voltage range. Superior performance can generally be
achieved by driving the reference pins with low impedance sources.
The circuit of Figure 31 will allow a more accurate setting of the reference voltages. The upper amplifier must be
able to source the reference current as determined by the value of the reference resistor and the value of (V_RT −
V_RB). The lower amplifier must be able to sink this reference current. Both should be stable with a capacitive
load. The LM8272 was chosen because of its rail-to-rail input and output capability, its high current output and its
ability to drive large capacitance loads.
The divider resistors at the inputs to the amplifiers could be changed to suit the application reference voltage
needs, or the divider can be replaced with potentiometers or DACs for precise settings. The bottom of the ladder
(V_RB) may be returned to ground if the minimum input signal excursion is 0V.
V_RT should always be more positive than V_RB by the minimum V_RT - V_RB difference in the Electrical
Characteristics table to minimize noise. Furthermore, the difference between V_RT and V_RB should not exceed the
maximum value specified in Converter Electrical Characteristics to avoid signal distortion.
The V_RM pin is the center of the reference ladder and should be bypassed to a clean, quiet point in the analog
ground plane with a 0.1 µF capacitor. DO NOT allow this pin to float.
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