TMS570LS3134_15 Datasheet, PDF (144/167 Pages) Texas Instruments – TMS570LS31x4/21x4 16- and 32-Bit RISC Flash Microcontroller

TMS570LS3134, TMS570LS2134, TMS570LS2124
SPNS165B – APRIL 2012 – REVISED MAY 2015
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7.9.4 MibSPI/SPI Master Mode I/O Timing Specifications
Table 7-22. SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO
= output, and SPISOMI = input)^(1)(2)(3)
NO.
1
t_c(SPC)M
t_w(SPCH)M
2 ⁽⁵⁾
t_w(SPCL)M
PARAMETER
Cycle time, SPICLK⁽⁴⁾
Pulse duration, SPICLK high (clock
polarity = 0)
Pulse duration, SPICLK low (clock
polarity = 1)
MIN
40
0.5t_c(SPC)M – t_r(SPC)M – 3
0.5t_c(SPC)M – t_f(SPC)M – 3
MAX UNIT
256t_c(VCLK) ns
0.5t_c(SPC)M + 3
ns
0.5t_c(SPC)M + 3
t_w(SPCL)M
3 ⁽⁵⁾
t_w(SPCH)M
Pulse duration, SPICLK low (clock
polarity = 0)
Pulse duration, SPICLK high (clock
polarity = 1)
0.5t_c(SPC)M – t_f(SPC)M – 3
0.5t_c(SPC)M – t_r(SPC)M – 3
0.5t_c(SPC)M + 3
ns
0.5t_c(SPC)M + 3
4 ⁽⁵⁾
t_{d(SPCH-SIMO)M}
Delay time, SPISIMO valid before
SPICLK low (clock polarity = 0)
0.5t_c(SPC)M – 6
ns
t_{d(SPCL-SIMO)M}
Delay time, SPISIMO valid before
SPICLK high (clock polarity = 1)
0.5t_c(SPC)M – 6
5 ⁽⁵⁾
t_{v(SPCL-SIMO)M}
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 0)
0.5t_c(SPC)M – t_f(SPC) – 4
ns
t_{v(SPCH-SIMO)M}
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 1)
0.5t_c(SPC)M – t_r(SPC) – 4
6 ⁽⁵⁾
t_{su(SOMI-SPCL)M}
Setup time, SPISOMI before SPICLK
low (clock polarity = 0)
t_f(SPC) + 2.2
ns
t_{su(SOMI-SPCH)M}
Setup time, SPISOMI before SPICLK
high (clock polarity = 1)
t_r(SPC) + 2.2
7 ⁽⁵⁾
t_{h(SPCL-SOMI)M}
Hold time, SPISOMI data valid after
SPICLK low (clock polarity = 0)
10
ns
t_{h(SPCH-SOMI)M}
Hold time, SPISOMI data valid after
SPICLK high (clock polarity = 1)
10
8 ⁽⁶⁾ t_C2TDELAY
9 ⁽⁶⁾ t_T2CDELAY
10 t_SPIENA
11 t_SPIENAW
Setup time CS active
until SPICLK high
(clock polarity = 0)
Setup time CS active
until SPICLK low
(clock polarity = 1)
CSHOLD = 0
CSHOLD = 1
CSHOLD = 0
CSHOLD = 1
C2TDELAY*t_c(VCLK) + 2*t_c(VCLK)
- t_f(SPICS) + t_r(SPC) – 7
C2TDELAY*t_c(VCLK) + 3*t_c(VCLK)
- t_f(SPICS) + t_r(SPC) – 7
C2TDELAY*t_c(VCLK) + 2*t_c(VCLK)
- t_f(SPICS) + t_f(SPC) – 7
C2TDELAY*t_c(VCLK) + 3*t_c(VCLK)
- t_f(SPICS) + t_f(SPC) – 7
(C2TDELAY+2) * t_c(VCLK) -
t_f(SPICS) + t_r(SPC) + 5.5
(C2TDELAY+3) * t_c(VCLK) -
t_f(SPICS) + t_r(SPC) + 5.5
ns
(C2TDELAY+2) * t_c(VCLK) -
t_f(SPICS) + t_f(SPC) + 5.5
(C2TDELAY+3) * t_c(VCLK) -
t_f(SPICS) + t_f(SPC) + 5.5
Hold time SPICLK low until CS inactive
(clock polarity = 0)
0.5*t_c(SPC)M +
T2CDELAY*t_c(VCLK) + t_c(VCLK) -
t_f(SPC) + t_r(SPICS) - 7
0.5*t_c(SPC)M +
T2CDELAY*t_c(VCLK) + t_c(VCLK) -
t_f(SPC) + t_r(SPICS) + 11
ns
Hold time SPICLK high until CS
inactive (clock polarity = 1)
0.5*t_c(SPC)M +
T2CDELAY*t_c(VCLK) + t_c(VCLK) -
t_r(SPC) + tr(SPICS) - 7
0.5*t_c(SPC)M +
T2CDELAY*t_c(VCLK) + t_c(VCLK) -
t_r(SPC) + t_r(SPICS) + 11
SPIENAn Sample point
(C2TDELAY+1) * t_c(VCLK) -
t_f(SPICS) – 29
(C2TDELAY+1)*t_c(VCLK) ^ns
SPIENAn Sample point from write to
buffer
(C2TDELAY+2)*t_c(VCLK) ^ns
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) t_c(VCLK) = interface clock cycle time = 1 / f_(VCLK)
(3) For rise and fall timings, see Table 5-7.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: t_c(SPC)M ≥ (PS +1)t_c(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: t_c(SPC)M = 2t_c(VCLK) ≥ 40 ns.
The external load on the SPICLK pin must be less than 60 pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
144 Peripheral Information and Electrical Specifications
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