TMS320C6678_16 Datasheet, PDF (140/247 Pages) Texas Instruments – Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691E—March 2014
7.6 Main PLL and PLL Controller
This section provides a description of the Main PLL and the PLL Controller. For details on the operation of the PLL
Controller module, see the Phase Locked Loop (PLL) for KeyStone Devices User Guide in ‘‘Related Documentation
from Texas Instruments’’ on page 72.
The Main PLL is controlled by the standard PLL Controller. The PLL controller manages the clock ratios, alignment,
and gating for the system clocks to the device. Figure 7-9 shows a block diagram of the main PLL and the PLL
Controller.
Figure 7-9 Main PLL and PLL Controller
CORECLK(N|P)
PLL
PLLD xPLLM
0
OUTPUT
DIVIDE
1
BYPASS
PLLOUT
PLL Controller
1
0
01
PLLEN 0
PLLENSRC
/1
PLLDIV1
/x
PLLDIV2
/2
PLLDIV3
/3
PLLDIV4
/y
PLLDIV5
/64
PLLDIV6
/6
PLLDIV7
/z
PLLDIV8
/12
PLLDIV9
/3
PLLDIV10
/6
PLLDIV11
SYSCLK1
SYSCLK2
C66x
CorePac
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
To Switch Fabric,
Peripherals,
Accelerators
SYSCLK8
SYSCLK9
SYSCLK10
SYSCLK11
140 Peripheral Information and Electrical Specifications
Copyright 2014 Texas Instruments Incorporated
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