TUSB8041-Q1 Datasheet, PDF (14/48 Pages) Texas Instruments – Automotive Four-Port USB 3.0 Hub

TUSB8041-Q1
SLLSEE6B – JULY 2014 – REVISED JANUARY 2016
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CONFIGURATION REGISTER
OFFSET
REG_07h
REG_0Ah
REG_0Ah
REG_0Bh
REG_0Bh
REG_0Bh
REG_0Bh
REG_F0h
Table 2. OTP Configurable Features (continued)
BIT FIELD
[3]
[3]
[4]
[0]
[1]
[2]
[3]
[3:1]
DESCRIPTION
Port removable configuration for downstream ports 4. OTP
configuration is inverse of rmbl[3:0], i.e. 1 = not removable, 0 =
removable.
Enable Device Attach Detection..
High-current divider mode enable.
USB 2.0 port polarity configuration for downstream ports 1.
USB 2.0 port polarity configuration for downstream ports 2.
USB 2.0 port polarity configuration for downstream ports 3.
USB 2.0 port polarity configuration for downstream ports 4.
USB power switch power-on delay.
8.3.4 Clock Generation
The TUSB8041-Q1 accepts a crystal input to drive an internal oscillator or an external clock source. If a clock is
provided to XI instead of a crystal, XO is left open. Otherwise, if a crystal is used, the connection needs to follow
the guidelines below. Since XI and XO are coupled to other leads and supplies on the PCB, it is important to
keep them as short as possible and away from any switching leads. It is also recommended to minimize the
capacitance between XI and XO. This can be accomplished by shielding C1 and C2 with the clean ground lines.
R1 1M
XI
TUSB8041 _XO
CLOCK
Y1
24 MHz
CL1
CL2
Figure 3. TUSB8041-Q1 Clock
8.3.5 Crystal Requirements
The crystal must be fundamental mode with load capacitance of 12 pF - 24 pF and frequency stability rating of
±100 PPM or better. To ensure proper startup oscillation condition, a maximum crystal equivalent series
resistance (ESR) of 50 Ω is recommended. A parallel load capacitor should be used if a crystal source is used.
The exact load capacitance value used depends on the crystal vendor. Refer to application note Selection and
Specification for Crystals for Texas Instruments USB2.0 devices (SLLA122) for details on how to determine the
load capacitance value.
8.3.6 Input Clock Requirements
When using an external clock source such as an oscillator, the reference clock should have a ±100 PPM or
better frequency stability and have less than 50-ps absolute peak to peak jitter or less than 25-ps peak to peak
jitter after applying the USB 3.0 jitter transfer function. XI should be tied to the 1.8-V clock source and XO should
be left floating.
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