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TPS74801-Q1_13 Datasheet, PDF (14/29 Pages) Texas Instruments – 1.5 A Low-Dropout Linear Regulator with Programmable Soft-Start
TPS74801-Q1
SLVSAI4B – OCTOBER 2010 – REVISED JULY 2013
www.ti.com
VIN
VBIAS
CIN
CBIAS
IN
OUT
BIAS TPS74801 FB
R
EN
GND
SS
C
R1
R2
CSS
VOUT
COUT
Figure 28. Soft-Start Delay Using an RC Circuit to Enable the Device
OUTPUT NOISE
The TPS74801-Q1 provides low output noise when a soft-start capacitor is used. When the device reaches the
end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 0.001-μF
soft-start capacitor, the output noise is reduced by half and is typically 30-μVRMS for a 1.2-V output (10 Hz to 100
kHz). Further increasing CSS has little effect on noise. Because most of the output noise is generated by the
internal reference, the noise is a function of the set output voltage. The RMS noise with a 0.001-μF soft-start
capacitor is given in Equation 3:
( ) VN(mVRMS) = 25 mVRMS x VOUT(V)
V
(3)
The low output noise of the TPS74801-Q1 makes it a good choice for powering transceivers, PLLs, or other
noise-sensitive circuitry.
ENABLE AND SHUTDOWN
The enable (EN) pin is active high and is compatible with standard digital signaling levels. VEN below 0.4 V turns
the regulator off, while VEN above 1.1 V turns the regulator on. Unlike many regulators, the enable circuitry has
hysteresis and deglitching for use with relatively slowly ramping analog signals. This configuration allows the
TPS74801-Q1 to be enabled by connecting the output of another supply to the EN pin. The enable circuitry
typically has 50 mV of hysteresis and a deglitch circuit to help avoid on-off cycling as a result of small glitches in
the VEN signal.
The enable threshold is typically 0.8 V and varies with temperature and process variations. Temperature
variation is approximately –1 mV/°C; process variation accounts for most of the rest of the variation to the 0.4-V
and 1.1-V limits. If precise turn-on timing is required, a fast rise-time signal must be used to enable the
TPS74801-Q1.
If not used, EN can be connected to either IN or BIAS. If EN is connected to IN, it should be connected as close
as possible to the largest capacitance on the input to prevent voltage droops on that line from triggering the
enable circuit.
POWER GOOD
The power good (PG) pin is an open-drain output and can be connected to any 5.5-V or lower rail through an
external pull-up resistor. This pin requires at least 1.1 V on VBIAS in order to have a valid output. The PG output is
high-impedance when VOUT is greater than VIT + VHYS. If VOUT drops below VIT or if VBIAS drops below 1.9 V, the
open-drain output turns on and pulls the PG output low. The PG pin also asserts when the device is disabled.
The recommended operating condition of PG pin sink current is up to 1 mA, so the pull-up resistor for PG should
be in the range of 10 kΩ to 1 MΩ. If output voltage monitoring is not needed, the PG pin can be left floating.
INTERNAL CURRENT LIMIT
The TPS74801-Q1 features a factory-trimmed, accurate current limit that is flat over temperature and supply
voltage. The current limit allows the device to supply surges of up to 2 A and maintain regulation. The current
limit responds in approximately 10 μs to reduce the current during a short-circuit fault.
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