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| TPS54561-Q1_16 Datasheet, PDF (14/51 Pages) Texas Instruments – TPS54561-Q1 4.5-V to 60-V Input, 5-A, Step-Down DC-DC Converter With Eco-mode | |||
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TPS54561-Q1
SLVSC60 â SEPTEMBER 2014
www.ti.com
Feature Description (continued)
⢠rDS(on) = 1 / (â0.3 à V(BOOT_SW)2 + 3.577 à V(BOOT_SW) â 4.246)
⢠V(BOOT_SW) = V(BOOT) + V(d)
⢠V(BOOT) = (1.41 à VImin â 0.554 â V(d) x f(SW) â 1.847 à 103 à I(BOOT_SW)) / (1.41 + f(SW))
⢠I(BOOT_SW) = 100 à 10-6 A
⢠f(SW) = Operating frequency in MHz
(1)
7.3.5 Error Amplifier
A transconductance error amplifier controls the TPS54561-Q1 voltage regulation loop. The error amplifier
compares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference.
The transconductance (gm(ea)) of the error amplifier is 350 µS during normal operation. During soft-start
operation, the device reduces the transconductance to 78 µS and references the error amplifier to the internal
soft-start voltage.
The frequency compensation components (capacitor, series resistor, and capacitor) connect the error-amplifier
output COMP pin to the GND pin.
7.3.6 Adjusting the Output Voltage
The internal voltage reference produces a precise 0.8-V ±1% voltage reference over the operating temperature
and voltage range by scaling the output of a bandgap reference circuit. A resistor divider from the output node to
the FB pin sets the output voltage. Divider resistors with a 1% tolerance or better are recommended. Select the
low-side resistor, R(LS), for the desired divider current, and use Equation 2 to calculate R(HS). To improve
efficiency at light loads, consider using larger-value resistors. However, if the values are too high, the regulator is
more susceptible to noise and voltage errors because of the FB input current may become noticeable.
R(HS)
=
R(LS)
´
æ
ç
è
VO - 0.8
0.8 V
V
ö
÷
ø
(2)
7.3.7 Enable and Adjust Undervoltage Lockout
The VDD pin voltage rising above 4.3 V when the EN pin voltage exceeds the enable threshold of 1.2 V enables
the TPS54561-Q1 device. The VDD pin voltage falling below 4 V or the EN pin voltage dropping below 1.2 V
disables the TPS54561-Q1 device. The EN pin has an internal pullup current source, I(1), of 1.2 µA that enables
operation of the TPS54561-Q1 device when the EN pin floats.
If an application requires a higher undervoltage lockout (UVLO) threshold, use the circuit shown in Figure 26 to
adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, the EN pin
sources an additional 3.4 µA of hysteresis current, I(HYS). This additional current facilitates adjustable input
voltage UVLO hysteresis. Pulling the EN pin below 1.2 V removes the 3.4-µA I(HYS) current. Use Equation 3 to
calculate R(UVLO1) for the desired UVLO hysteresis voltage. Use Equation 4 to calculate R(UVLO2) for the desired
VDD start voltage.
In applications designed to start at relatively low input voltages (for example, from 4.5 V to 9 V) and withstand
high input voltages (for example, from 40 V to 60 V), the EN pin may experience a voltage greater than the
absolute maximum voltage of 8.4 V during the high-input-voltage condition. To avoid exceeding this voltage
when using the EN resistors, a 5.8-V Zener diode that is capable of sinking up to 150 µA internally clamps the
EN pin.
R(UVLO1) =
æ
ççè
V(START) - V(STOP)
I (HYS )
ö
÷÷ø
(3)
R(UVLO2) =
V(EN)th
V(START) - V(EN)th
R (UVLO1)
+ I(1)
(4)
14
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