TPS53632G_16 Datasheet, PDF (14/41 Pages) Texas Instruments – D-CAP+™ Half-Bridge PWM Controller Optimized for GaN-based 48-V DC/DC Converter with I2C Interface

TPS53632G
SLUSCJ3A – APRIL 2016 – REVISED JUNE 2016
Feature Description (continued)
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UDG-13051
Figure 10. Master Code Sequence
7.3.11 Start-Up Sequence
The TPS53632G initializes when all of the supply voltages rise above the UVLO thresholds. This function is also
know as a cold boot. The device then reads all of the various settings (such as frequency and overcurrent
protection). This process takes less than 1.2 ms. During this time, the VSR pin initializes to the BOOT voltage.
The output voltage rises to the voltage select register (VSR) level when the EN pin (enable) goes high. As soon
as the BOOT sequence completes, PGOOD is HIGH and the I²C interface can be used to change the voltage
select register. The current VSR value is held when EN goes low and returns to a high state This function is also
know as a warm boot). The VSR can be changed when EN is low, however, this is not recommended prior to
completion of the cold boot process.
7.3.12 Power Good Operation
PGOOD is an open-drain output pin that is designed to be pulled up with an external resistor to a voltage 3.6 V
or less. Normal PGOOD operation (exclusive of OC or MAXVID interrupt action) is shown in Figure 11. On initial
power-up, a power good status occurs within 6 µs of the DAC reaching its target value. When EN is brought low,
the PGOOD pin is also brought low for 250 µs and then is allowed to float. The TPS53632G device pulls down
the PGOOD signal when the EN signal subsequently goes high and returns high again within 6 µs of the end of
the DAC ramp. The delay period between the EN pin going high and the PGOOD pin going low in this case is
less than 1 µs.
Figure 11 shows the power good operation at initial start up and with falling and rising EN.
VBIAS
VOUT
EN
PGOOD
1 Ps
1.2 ms
6 Ps
250 Ps
250 Ps
Figure 11. Power Good Operation
UDG-13096
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