TPS40042_16 Datasheet, PDF (14/36 Pages) Texas Instruments – LOW PIN COUNT, LOW VIN (3.0 V TO 5.5 V) SYNCHRONOUS BUCK DC-TO-DC CONTROLLER WITH EXTERNAL REFERENCE INPUT

TPS40042
SLUS777 – NOVEMBER 2007
www.ti.com
Total Gate Charge
The internal voltage sensing of the external MOSFET gate voltages used by the TPS40042 to control the
dead-times between turn-off and turn-on can be sensitive to large MOSFET gate charges, especially when
different gate charges are used for the high-side and low-side MOSFETs. Increased gate charge increases
MOSFET switching times and decreases the dead-time between the MOSFETs switching.
DESIGN
HINT:
MOSFETs with no more than 40 nC of total gate charge should be selected.
The upper switch MOSFET’s gate charge should be no less than 60% of the
synchronous rectifier’s gate charge to minimize the turn-on/turn-off delay
mismatch between the high-side and low-side MOSFET.
Synchronous Rectifier dV/dt Turn-On
As the upper switch MOSFET turns on, the switch node voltage rises from close to ground to VIN in a very short
period of time (typically 10 ns to 30 ns) resulting in very high voltage spikes on the switch node. The construction
of a MOSFET creates parasitic capacitances between its terminals, particularly the gate-to-drain and
gate-to-source, creating a capacitive divider between the drain and source of the MOSFET with the gate at its
mid-point. If the gate-to-drain charge (Q_GD) is larger than the gate-to-source charge (Q_GS), the capacitive divider
places proportionally more charge on the gate of the MOSFET as the switch node voltage rises than is shunted
to GND. In extreme cases, this can cause the synchronous rectifier gate voltage to rise above the turn on
threshold voltage of the MOSFET and causes cross-conduction. This is called dV/dt turn-on. It increases power
dissipation in both the high-side and the low-side MOSFET, reducing efficiency.
DESIGN
HINT:
Select a synchronous rectifier MOSFET with a Q_GD to Q_GS ratio of less than
one and provide a wide, low resistance, low inductance loop in the synchronous
rectifier gate drive circuit. (See Layout Consideration)
DESIGN
HINT:
A resistor in series with the boost capacitor slows the turn on of the high-side
MOSFET, and reduces the dV/dt of the switch node. See Boost Capacitor
Series Resistor section.
Bootstrap for N-Channel MOSFET Drive
The PWM duty cycle is limited to a maximum of 95%, allowing the bootstrap capacitor to charge during every
cycle. During each PWM OFF period, the voltage on VDD charges the bootstrap capacitor. When the PWM
switch is next commanded to turn ON, the voltage used to drive the MOSFET is derived from the voltage on this
capacitor. Since this is a charge transfer circuit, the value of the bootstrap capacitor must be sized such that the
energy stored in the capacitor on a per cycle basis is greater then the gate charge requirement of the MOSFET
being used. See the Design Example section for details.
Bootstrap Capacitor Series Resistor
Since resistors should not be placed in series with the high-side gate, it may be necessary to place a small 1-Ω
to 3-Ω resistor in series with the bootstrap capacitor to control the turn-on of the main switching MOSFET and
reduce the dV/dt rate of rise of the switch node voltage. A resistor placed between the BOOT pin and the
bootstrap capacitor increases the series resistance during the turn-on of the high-side MOSFET, and has no
effect during the high-side MOSFET’s turn-off period. This prevents the TPS40042 from sensing the upper switch
MOSFET’s turn-off too early and reducing the upper switch MOSFET turn-off to the SR MOSFET turn-on delay
timing too far.
DESIGN To reduce EMI, place a small 1-Ω to 3-Ω resistor in series with the boost
HINT: capacitor to control the turn-on of the main switching FET.
External Schottky Diode for Low Input Voltage
The TPS40042 uses an internal P-channel MOSFET switch between VDD and BOOT to charge the bootstrap
capacitor during synchronous rectifier conduction time. At low input voltages, a MOSFET can not be turned on
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