THS4082 Datasheet, PDF (14/32 Pages) National Semiconductor (TI) – 175 MHz High Speed AMPLIFIERS

THS4081, THS4082
ą
175ĆMHz LOWĆPOWER HIGHĆSPEED AMPLIFIERS
SLOS274D − DECEMBER 1999 − REVISED JUNE 2001
APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS408x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 41. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
1.3 kΩ
Input
1.3 kΩ
_
THS408x
+
20 Ω
Output
CLOAD
Figure 41. Driving a Capacitive Load
offset voltage
The output offset voltage, (V_OO) is the sum of the input offset voltage (V_IO) and both input bias currents (I_IB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
RF
IIB−
RG
+
−
VI
+
VO
RS
IIB+
ǒ ǒ ǓǓ ǒ ǒ ǓǓ VOO + VIO
1)
RF
RG
" IIB₎ RS
1)
RF
RG
" IIB– RF
Figure 42. Output Offset Voltage Model
14
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265