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SLK2511C_13 Datasheet, PDF (14/22 Pages) Texas Instruments – OC-48/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER
SLK2511C
SLLS886 – DECEMBER 2008............................................................................................................................................................................................ www.ti.com
TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
REFERENCE CLOCK (REFCLK)
Frequency tolerance(1)
Duty cycle
Jitter
12 kHz to 20 MHz
PLL PERFORMANCE SPECIFICATIONS
PLL startup lock time
Acquisition lock time
VDD, VDDC = 2.3 V, after REFCLK is stable
Valid SONET signal or PRBS OC-48
SERIAL TRANSMITTER/RECEIVER CHARACTERISTICS
V(ODD) = |STXDOP-STXDON|, transmit
differential output voltage under
de-emphasis
PRE1 = 0, PRE2 = 0, Rt = 50,
See Table 5 and Figure 1
PRE1 = 1, PRE2 = 0
PRE1 = 0, PRE2 = 1
PRE1 = 1, PRE2 = 1
V(CMT) Transmit common mode voltage range
Receiver Input voltage requirement,
VID=|SRXDIP–SRXDIN|
V(CMR) Receiver common mode voltage range
Il
Receiver input leakage
Rl
Receiver differential impedance
CI
Receiver input capacitance
td(TX_Laten
cy)
td(RX_Late
ncy)
Rt = 50Ω
MIN TYP MAX UNIT
–20
40%
50%
20
60%
3
ppm
ps rms
2031
1 ms
Bit Times
650 850 1000
550 750 900 mV
540 700 860
500 650 800
1100 1250 1400 mV
150
mV
1100
-550
80
1250
100
2250 mV
550 µA
120 Ω
1 pF
50
Bit Times
50
(1) The ±20 ppm tolerance is required to meet SONET/SDH requirements. For non-SONET/SDH compliant systems, looser tolerances may
apply.
SERIAL DIFFERENTIAL SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tt Differential signal rise time (20% to 80%) RL = 50Ω
tj Output jitter
Jitter-free data, 12 kHz to 20 MHz, RLOOP = 1
Jitter tolerance
RLOOP = 1, See Figure 2, Figure 12
Jitter transfer
RLOOP = 1, See Figure 2
MIN TYP MAX UNIT
80 100 140 ps
0.05
0.1 UI(pp)
14
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