OPT3001-Q1 Datasheet, PDF (14/43 Pages) Texas Instruments – Ambient Light Sensor (ALS)

OPT3001-Q1
SBOS853 – MARCH 2017
www.ti.com
Device Functional Modes (continued)
Table 2. Latched Window-Style Comparison Mode: Flag Setting and Clearing Summary⁽¹⁾⁽²⁾
OPERATION
The result register is above the high-limit register for fault count times.
See the Result Register and the High-Limit Register for further details.
The result register is below the low-limit register for fault count times.
See the Result Register and the Low-Limit Register for further details.
The conversion is complete with fault count criterion not met
Configuration register read⁽⁴⁾
Configuration register write, M[1:0] = 00b (shutdown)
Configuration register write, M[1:0] > 00b (not shutdown)
SMBus alert response protocol
FLAG HIGH
FIELD
1
FLAG LOW
FIELD
X
X
1
X
X
0
0
X
X
X
X
X
X
INT PIN⁽³⁾
Active
CONVERSION
READY FIELD
1
Active
1
X
1
Inactive
0
X
X
X
0
Inactive
X
(1) X = no change from the previous state.
(2) The high-limit register is assumed to be greater than the low-limit register. If this assumption is incorrect, the flag high field and flag low
field can take on different behaviors.
(3) The INT pin depends on the setting of the polarity field (POL). The INT pin is low when the pin state is active and POL = 0 (active low)
or when the pin state is inactive and POL = 1 (active high).
(4) Immediately after the configuration register is read, the device automatically resets the conversion ready field to its 0 state. Thus, if two
configuration register reads are performed immediately after a conversion completion, the first reads 1 and the second reads 0.
7.4.2.2 Transparent Hysteresis-Style Comparison Mode
The transparent hysteresis-style comparison mode is typically used when a single digital signal is desired that
indicates whether the input light is higher than or lower than a light level of interest. If the result register is higher
than the high-limit register for a consecutive number of events set by the fault count field, the INT line is set to
active, the flag high field is set to 1, and the flag low field is set to 0. If the result register is lower than the low-
limit register for a consecutive number of events set by the fault count field, the INT line is set to inactive, the flag
low field is set to 1, and the flag high field is set to 0. The INT pin and flag high and flag low fields do not change
state with configuration reads and writes. The INT pin and flag fields continually report the appropriate
comparison of the light to the low-limit and high-limit registers. The device does not respond to the SMBus alert
response protocol while in either of the two transparent comparison modes (configuration register, latch field =
0). The behavior of this mode, along with the conversion ready is summarized in Table 3. Note that Table 3 does
not apply when the two threshold low register MSBs (LE[3:2] from Table 11) are set to 11.
Table 3. Transparent Hysteresis-Style Comparison Mode: Flag Setting and Clearing Summary⁽¹⁾⁽²⁾
OPERATION
The result register is above the high-limit register for fault count times.
See the Result Register and the High-Limit Register for further details.
The result register is below the low-limit register for fault count times.
See the Result Register and the Low-Limit Register for further details.
The conversion is complete with fault count criterion not met
Configuration register read⁽⁴⁾
Configuration register write, M[1:0] = 00b (shutdown)
Configuration register write, M[1:0] > 00b (not shutdown)
SMBus alert response protocol
FLAG HIGH
FIELD
1
FLAG LOW
FIELD
0
0
1
X
X
X
X
X
X
X
X
X
X
INT PIN⁽³⁾
Active
CONVERSION
READY FIELD
1
Inactive
1
X
1
X
0
X
X
X
0
X
X
(1) X = no change from the previous state.
(2) The high-limit register is assumed to be greater than the low-limit register. If this assumption is incorrect, the flag high field and flag low
field can take on different behaviors.
(3) The INT pin depends on the setting of the polarity field (POL). The INT pin is low when the pin state is active and POL = 0 (active low)
or when the pin state is inactive and POL = 1 (active high).
(4) Immediately after the configuration register is read, the device automatically resets the conversion ready field to its 0 state. Thus, if two
configuration register reads are performed immediately after a conversion completion, the first reads 1 and the second reads 0.
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