OPA689 Datasheet, PDF (14/20 Pages) Burr-Brown (TI) – Wideband, High Gain VOLTAGE LIMITING AMPLIFIER

ESD PROTECTION
ESD damage is known to damage MOSFET devices, but any
semiconductor device is vulnerable to ESD damage. This is
particularly true for very high speed, fine geometry processes.
ESD damage can cause subtle changes in amplifier input
characteristics without necessarily destroying the device. In
precision operational amplifiers, this may cause a noticeable
degradation of offset voltage and drift. Therefore, ESD
handling precautions are required when handling the OPA689.
OUTPUT LIMITERS
The output voltage is linearly dependent on the input(s)
when it is between the limiter voltages V_H (pin 8) and V_L
(pin 5). When the output tries to exceed V_H or V_L, the
corresponding limiter buffer takes control of the output
voltage and holds it at V_H or V_L.
Because the limiters act on the output, their accuracy does
not change with gain. The transition from the linear region
of operation to output limiting is sharp—the desired output
signal can safely come to within 30mV of V_H or V_L.
Distortion performance is also good over the same range.
The limiter voltages can be set to within 0.7V of the supplies
(V_L ≥ –V_S + 0.7V, V_H ≤ +V_S – 0.7V). They must also be at
least 200mV apart (V_H – V_L ≥ 0.2V).
When pins 5 and 8 are left open, V_H and V_L go to the Default
Voltage Limit; the minimum values are in the spec table.
Looking at Figure 7 for the zero bias current case will show
the expected range of (V_S – default limit voltages) = head-
room).
When the limiter voltages are more than 2.1V from the
supplies (V_L ≥ –V_S + 2.1V or V_H ≤ +V_S – 2.1V), you can
use simple resistor dividers to set V_H and V_L (see Figure 1).
Make sure you include the Limiter Input Bias Currents
(Figure 7) in the calculations (i.e., I_VL ≈ –50µA out of pin
5, and I_VH ≈ +50µA out of pin 8). For good limiter voltage
accuracy, run at least 1mA quiescent bias current through
these resistors.
LIMITER INPUT BIAS CURRENT vs BIAS VOLTAGE
100
Maximum Over Temperature
75
50
25
Minimum Over Temperature
0
–25
–50
Limiter Headroom = +V_S – V_H
= V_L – (–V_S)
–75
Current = I_VH or –I_VL
–100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Limiter Headroom (V)
When the limiter voltages need to be within 2.1V of the
supplies (V_L ≤ –V_S + 2.1V or V_H ≥ +V_S – 2.1V), use low
impedance voltage sources to set V_H and V_L to minimize
errors due to bias current uncertainty. This will typically be
the case for single supply operation (V_S = +5V). Figure 2
runs 2.5mA through the resistive divider that sets V_H and
V_L. This keeps errors due to I_VH and I_VL < ±1% of the target
limit voltages.
The limiters’ DC accuracy depends on attention to detail.
The two dominant error sources can be improved as follows:
• Power supplies, when used to drive resistive dividers that
set V_H and V_L, can contribute large errors (e.g., (5%).
Using a more accurate source, or bypassing pins 5 and 8
with good capacitors, will improve limiter PSRR.
• The resistor tolerances in the resistive divider can also
dominate. Use 1% resistors.
Other error sources also contribute, but should have little
impact on the limiters’ DC accuracy:
• Reduce offsets caused by the Limiter Input Bias Currents.
Select the resistors in the resistive divider(s) as described
above.
• Consider the signal path DC errors as contributing to the
uncertainty in the useable output range.
• The Limiter Offset Voltage only slightly degrades the
limiter accuracy.
Figure 8 shows how the limiters affect distortion perfor-
mance. Virtually no degradation in linearity is observed for
output voltages swinging right up to the limiter voltages.
HARMONIC DISTORTION NEAR LIMIT VOLTAGES
–40
–45
V_O = 0V_DC ±1Vp
–50
f₁ = 5MHz
R_L = 500Ω
–55
HD2
–60
–65
–70
–75
–80
HD3
–85
–90
0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
± Limit Voltage (V)
FIGURE 8. Linearity Guardband.
FIGURE 7. Limiter Bias Current vs Limiter Voltage.
®
OPA689
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