LMZ23608_14 Datasheet, PDF (14/29 Pages) Texas Instruments – 8A SIMPLE SWITCHER® Power Module with 36V Maximum Input Voltage and Current Sharing

LMZ23608
SNVS708D – MARCH 2011 – REVISED OCTOBER 2011
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The LMZ23608 typical application shows 12.7kΩ for R_ENB and 42.2kΩ for R_ENT resulting in a rising UVLO of
5.51V. Note that this divider presents 4.62V to the EN input when V_IN is raised to 20V. This upper voltage should
always be checked, making sure that it never exceeds the Abs Max 5.5V limit for Enable. A 5.1V Zener clamp
can be applied in cases where the upper voltage would exceed the EN input's range of operation. The zener
clamp is not required if the target application prohibits the maximum Enable input voltage from being exceeded.
Additional enable voltage hysteresis can be added with the inclusion of R_ENH. It is possible to select values for
R_ENT and R_ENB such that R_ENH is a value of zero allowing it to be omitted from the design.
Rising threshold can be calculated as follows:
V_EN(rising) = 1.274 ( 1 + (R_ENT|| 2 meg)/ R_ENB)
(2)
Whereas the falling threshold level can be calculated using:
V_EN(falling) = V_EN(rising) – 13 µA ( R_ENT|| 2 meg || R_ENTB + R_ENH )
(3)
5.1V
VIN
RENT
42.2k
RENH
100:
RENB
12.7k
ENABLE
INT-VCC (5V)
2.0M
13 PA
1.274V
RUN
Figure 4. Enable input detail
OUTPUT VOLTAGE SELECTION
Output voltage is determined by a divider of two resistors connected between V_OUT and AGND. The midpoint of
the divider is connected to the FB input.
The regulated output voltage determined by the external divider resistors R_FBT and R_FBB is:
V_OUT = 0.795V * (1 + R_FBT / R_FBB)
(4)
Rearranging terms; the ratio of the feedback resistors for a desired output voltage is:
R_FBT / R_FBB = (V_OUT / 0.795V) - 1
(5)
These resistors should generally be chosen from values in the range of 1.0 kΩ to 10.0 kΩ.
For V_OUT = 0.8V the FB pin can be connected to the output directly and R_FBB can be set to 8.06kΩ to provide
minimum output load.
A table of values for R_FBT , and R_FBB, is included in the simplified applications schematic on page 2.
SOFT-START CAPACITOR SELECTION
Programmable soft-start permits the regulator to slowly ramp to its steady state operating point after being
enabled, thereby reducing current inrush from the input supply and slowing the output voltage rise-time.
Upon turn-on, after all UVLO conditions have been passed, an internal 1.6msec circuit slowly ramps the SS input
to implement internal soft start. If 1.6 msec is an adequate turn–on time then the Css capacitor can be left
unpopulated. Longer soft-start periods are achieved by adding an external capacitor to this input.
Soft start duration is given by the formula:
t_SS = V_REF * C_SS / Iss = 0.795V * C_SS / 50uA
(6)
This equation can be rearranged as follows:
C_SS = t_SS * 50μA / 0.795V
(7)
14
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