LMK00725 Datasheet, PDF (14/23 Pages) Texas Instruments – Low Skew, 1-to-5, Differential-to-3.3V LVPECL Fanout Buffer

LMK00725
SNAS625A – SEPTEMBER 2013 – REVISED OCTOBER 2013
www.ti.com
Recommendations for Unused Input and Output Pins
• CLK_SEL and CLK_EN: These inputs have internal pull-up (R_PU) or pull-down (R_PD) according to Figure 1
and can be left floating if unused. The floating state for CLK_SEL is channel 0 selected, and the default for
CLK-EN is normal output.
• CLK/nCLK inputs: See Figure 21 for the internal connections. When using single ended input, take note of
the internal pull-up and pull-down to make sure the unused input is properly biased. For single ended input,
the Figure 10 arrangement is recommended.
• Outputs: Unused outputs can be left floating or terminated. If left floating, it is recommended to not attach
any traces to the output pins.
Input Slew Rate Considerations
LMK00725 employs high-speed and low-latency circuit topology, allowing the device to achieve ultra-low additive
jitter/phase noise and high-frequency operation. To take advantage of these benefits in the system application, it
is optimal for the input signal to have a high slew rate of 3 V/ns or greater. Driving the input with a slower slew
rate can degrade the additive jitter and noise floor performance. For this reason, a differential signal input is
recommended over single-ended because it typically provides higher slew rate and common-mode-rejection.
Refer to the “Additive RMS Jitter vs. Input Slew Rate” plots in the TYPICAL CHARACTERISTICS section. Also,
using an input signal with very slow input slew rate, such as less than 0.05 V/ns, has the tendency to cause
output switching noise to feed-back to the input stage and cause the output to chatter. This is especially true
when driving either input in single-ended fashion with a very slow slew rate, such as a sine-wave input signal.
System-Level Phase Noise and Additive Jitter Measurement
For high-performance devices, limitations of the equipment influence phase-noise measurements. The noise floor
of the equipment is often higher than the noise floor of the device. The real noise floor of the device is probably
lower. It is important to understand that system-level phase noise measured at the DUT output is influenced by
the input source and the measurement equipment.
For Figure 25 and Figure 26 system-level phase noise plots, a Rohde & Schwarz SMA100A low-noise signal
generator was cascaded with an Agilent 70429A K95 single-ended to differential converter block with ultra-low
phase noise and fast edge slew rate (>3 V/ns) to provide a very low-noise clock input source to the LMK00725.
An Agilent E5052 source signal analyzer with ultra-low measurement noise floor was used to measure the phase
noise of the input source (SMA100A + 70429A K95) and system output (input source + LMK00725). The input
source phase noise is shown by the light yellow trace, and the system output phase noise is shown by the dark
yellow trace.
The additive phase noise or noise floor of the buffer (PN_FLOOR) can be computed as follows:
PN_FLOOR (dBc/Hz) = 10*log₁₀[10^(PN_SYSTEM/10) – 10^(PN_SOURCE/10)]
where
• PN_SYSTEM is the phase noise of the system output (source+buffer)
• PN_SOURCE is the phase noise of the input source
(1)
space
The additive jitter of the buffer (J_ADD) can be computed as follows:
J_ADD = SQRT(J_SYSTEM2– J_SOURCE2),
where
• J_SYSTEM is the RMS jitter of the system output (source+buffer), integrated from 10 kHz to 20 MHz
• J_SOURCE is the RMS jitter of the input source, integrated from 10 kHz to 20 MHz
(2)
14
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