BQ2014_15 Datasheet, PDF (14/27 Pages) Texas Instruments – Gas Gauge IC with External Charge Control

Not Recommended For New Designs
bq2014
The CR values are:
FLGS2 Bits
7
65
4
3
2
1
0
CR - -
-
-
-
-
-
Where CR is:
0 When charge rate falls below 2 counts/sec
1 When charge rate is above 2 counts/sec
The fast charge regime efficiency factors are used when
CR = 1. When CR = 0, the trickle charge efficiency fac-
tors are used. The time to change CR varies due to the
user-selectable count rates.
The discharge rate flags, DR2–0, are bits 6–4.
FLGS2 Bits
7
6
5
4
3210
-
DR2 DR1 DR0 - - -
They are used to determine the current discharge re-
gime as follows:
DR2
0
0
DR1
0
0
DR0
0
1
VSR (V)
VSR > -150mV
VSR < -150mV
The overload flag (OVLD) is asserted when a discharge
overload is detected, VSR < -250mV. OVLD remains as-
serted as long as the condition persists and is cleared af-
ter VSR > -150mV. The overload condition is used to stop
sampling of the battery terminal characteristics for
end-of-discharge determination when excessive dis-
charges occur.
FLGS2 Bits
7
65
4
3
2
-
--
-
-
-
1
0
- OVLD
DR2–0 and OVLD are set based on the measurement of the
voltage at the SR pin relative to VSS. The rate at which
this measurement is made varies with device activity.
Program Pin Pull-Down Register (PPD)
The read-only PPD register (address=07h) contains some
of the programming pin information for the bq2014. The
segment drivers, SEG1–5 and DONE, have corresponding
PPD register locations, PPD1–6. A given location is set if a
pull-down resistor has been detected on its corresponding
segment driver. For example, if SEG1 and SEG4 have
pull-down resistors, the contents of PPD are xx101001.
(Note: DONE must be pulled down for proper operation.)
Program Pin Pull-Up Register (PPU)
The read-only PPU register (address=08h) contains the
rest of the programming pin information for the bq2014.
The segment drivers, SEG1–5 and DONE, have corre-
sponding PPU register locations, PPU1–6. A given loca-
tion is set if a pull-up resistor has been detected on its
corresponding segment driver. For example, if SEG3 and
DONE have pull-up resistors, the contents of PPU are
xx100100.
PPD/PPU Bits
8
7
6
5
4
3
2
1
-
- PPU6 PPU₅ PPU4 PPU3 PPU2 PPU1
-
- PPD6 PPD₅ PPD4 PPD3 PPD2 PPD1
Capacity Inaccurate Count Register (CPI)
The read-only CPI register (address=09h) is used to in-
dicate the number of times a battery has been charged
without an LMD update. Because the capacity of a re-
chargeable battery varies with age and operating condi-
tions, the bq2014 adapts to the changing capacity over
time. A complete discharge from full (NAC=LMD) to
empty (EDV1=1) is required to perform an LMD update
assuming there have been no intervening valid charges,
the temperature is greater than or equal to 0°C, and the
self-discharge counter is less than 4096 counts.
The CPI register is incremented every time a valid
charge is detected. When NAC > 0.94 ∗ LMD, however,
the CPI register increments on the first valid charge;
CPI does not increment again for a valid charge until
NAC < 0.94 ∗ LMD. This prevents continuous trickle
charging from incrementing CPI if self-discharge decre-
ments NAC. The CPI register increments to 255 with-
out rolling over. When the contents of CPI are incre-
mented to 64, the capacity inaccurate flag, CI, is as-
serted in the FLGS1 register. The CPI register is reset
whenever an update of the LMD register is performed,
and the CI flag is also cleared.
Digital Magnitude Filter (DMF)
The read-write DMF register (address=0Ah) provides
the system with a means to change the default settings
of the digital magnitude filter. By writing different val-
ues into this register, the limits of VSRD and VSRQ can be
adjusted.
Note: Care should be taken when writing to this regis-
ter. A VSRD and VSRQ below the specified VOS may ad-
versely affect the accuracy of the bq2014. Refer to Table
4 for recommended settings for the DMF register.
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