ADS8329_14 Datasheet, PDF (14/51 Pages) Texas Instruments – LOW-POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE

ADS8329
ADS8330
SLAS516C – DECEMBER 2006 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com
SCLK
CS/FS
SDO
Hi−Z
1
2
3
4
5
6
7
14
15
16
t_{su(CSF−SCLK1F)}
t_wL(SCLK)
t_c(SCLK)
t_wH(SCLK)
t_{d(CSF−SDOVALID)}
t_{d(SCLKF−SDOINVALID)}
t_{d(CSR−SDOZ)}
t_{d(SCLKF−SDOVALID)}
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6
LSB+2 LSB+1 LSB
t_{su(16thSCLK−CSR)}
SDI
MSB
t_{h(SDI−SCLKF)}
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−6
t_{su(SDI−SCLKF)}
LSB+2 LSB+1 LSB
Figure 5. Detailed SPI Transfer Timing
MANUAL TRIGGER / READ While Sampling
(use internal CCLK active high, EOC and INT active low, TAG enabled, auto channel select)
Nth CH0
Nth CH1
CONVST
t_wL(CONVST)
t_wL(CONVST)
EOC
(active low)
INT
(active low)
CS/FS
Nth CH0
t_CONV = 18 CCLKs
t_SAMPLE1 = 3 CCLKs min
t_su(CSF-EOS)
t_h(CSF-EOC)
Nth CH1
t_CONV = 18 CCLKs
SCLK
SDO
SDI
Hi−Z
1 . . . . . . . . . . . . . . . . . . . . . . . 16 17
N−1st CH1
1101b
READ Result
TAG = 1
1 . . . . . . . . . . . . . . . . . . . . . . . 16 17
t_d(CSR-EOS) = 20 ns MIN
Nth CH0
Hi−Z
TAG = 0
1101b
READ Result
Figure 6. Simplified Dual Channel Timing
14
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