ADS8323_14 Datasheet, PDF (14/26 Pages) Texas Instruments – 16-Bit, 500kSPS, microPower Sampling ANALOG-TO-DIGITAL CONVERTER

ADS8323
SBAS224C – DECEMBER 2001 – REVISED JANUARY 2010
NOISE
Figure 20 shows the transition noise of the ADS8323.
A low-level dc input was applied to the analog-input
pins and the converter was put through 8192
conversions. The digital output of the ADC varies in
output code due to the internal noise of the ADS8323.
This characteristic is true for all 16-bit SAR-type
ADCs. The ADS8323, with five output codes for the σ
distribution, yields a greater than ±0.8LSB transition
noise at 5V operation. Remember that to achieve this
low-noise performance, the peak-to-peak noise of the
input signal and reference must be less than 50μV.
5052
1968
818
300
54
0014
0015
0016
Code
0017
0018
Figure 20. Histogram of 8,192 Conversions of a
Low-Level DC Input
AVERAGING
Averaging the digital codes can compensate the
noise of the ADC. By averaging conversion results,
transition noise is reduced by a factor of 1/√n, where
n is the number of averages. For example, averaging
four conversion results reduces the transition noise
by 1/2 to ±0.4LSB. Averaging should only be used for
input signals with frequencies near dc. For ac signals,
a digital filter can be used to low-pass filter and
decimate the output codes. This process works in a
similar manner to averaging—for every decimation by
2, the signal-to-noise ratio improves by 3dB.
BIPOLAR INPUTS
The differential inputs of the ADS8323 were designed
to accept bipolar inputs (–V_REF and +V_REF) around the
common-mode voltage, which corresponds to a 0V to
5V input range with a 2.5V reference. By using a
simple op amp circuit featuring four high-precision
external resistors, the ADS8323 can be configured to
accept bipolar inputs. The conventional ±2.5V, ±5V,
and ±10V input ranges could be interfaced to the
ADS8323 using the resistor values shown in
Figure 21.
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R₁
Bipolar
Input
4kW
20kW
OPA132
R₂
OPA353
BIPOLAR INPUT
R₁
±10V
1kW
±5V
2kW
±2.5V
4kW
R₂
5kW
10kW
20kW
+IN (pin 26)
-IN (pin 25)
ADS8323
REF_OUT (pin 32)
2.5V
Figure 21. Level Shift Circuit for Bipolar Input
Ranges
DIGITAL INTERFACE
TIMING AND CONTROL
See the timing diagram and the Timing
Characteristics section for detailed information on
timing signals and the respective requirements for
each.
The ADS8323 uses an external clock (CLOCK, pin
20) that controls the conversion rate of the CDAC.
With a 10MHz external clock, the ADC sampling rate
is 500kSPS that corresponds to a 2μs maximum
throughput time.
Conversions are initiated by bringing the CONVST
pin low for a minimum of 20ns (after the 20ns
minimum requirement has been met, the CONVST
pin can be brought high), while CS is low. The
ADS8322 switches from Sample-to-Hold mode on the
falling edge of the CONVST command. Following the
first rising edge of the external clock after a CONVST
low, the ADS8322 begins conversion (this first rising
edge of the external clock represents the start of
clock cycle one; the ADS8322 requires 16 rising clock
edges to complete a conversion). The BUSY output
goes high immediately following CONVST going low.
BUSY stays high through the conversion process and
returns low when the conversion has ended.
Both RD and CS can be high during and before a
conversion (although CS must be low when CONVST
goes low to initiate a conversion). Both the RD and
CS pins are brought low in order to enable the
parallel output bus with the conversion.
14
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