ADS807_14 Datasheet, PDF (14/22 Pages) Texas Instruments – 12-Bit, 53MHz Sampling ANALOG-TO-DIGITAL CONVERTER

INPUT
REFERENCE IN (Pin-25) IN (Pin-24) REFT REFB
2Vp-p Differential
Internal
1Vp-p Times 2 Inputs or External
2V to 3V
3V to 2V +3V +2V
2Vp-p Single-Ended
2Vp-p Times 1 Input
Internal 1.5V to 3.5V
or External
2.5V_DC
+3V +2V
3Vp-p Differential
Internal 1.75V to 3.35V 3.25V to 1.75V +3.25V +1.75V
1.5Vp-p Times 2 Inputs or External
3Vp-p Single-Ended
3Vp-p Times 1 Input
Internal
or External
1V to 4V
2.5V_DC +3.25V +1.75V
TABLE I. Reference Voltages for Input Signal Ranges.
If it is desired to switch between internal and external refer-
ences, disconnect switches must be added between the exter-
nal references and the ADS807.
DIGITAL INPUTS AND OUTPUTS
Clock Input Requirements
Clock jitter is critical to the SNR performance of high-speed,
high-resolution A/D converters. Clock jitter leads to aperture
jitter (t_A), which adds noise to the signal being converted. The
ADS807 samples the input signal on the rising edge of the CLK
input. Therefore, this edge should have the lowest possible
jitter. The jitter noise contribution to total SNR is given by the
following equation. If this value is near your system require-
ments, input clock jitter must be reduced.
Jitter SNR = 20 log ¹ rms signal to rms noise
2πƒ_IN t_A
where: ƒ_IN is input signal frequency
t_A is rms clock jitter
Particularly in undersampling applications, special consider-
ation should be given to clock jitter. The clock input should be
treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should have
50% duty cycle (t_H = t_L), along with fast rise and fall times of
2ns or less.
Over-Range Indicator (OTR)
If the analog input voltage exceeds the set full-scale range,
an over-range condition exists. The ‘OTR’ pin of the ADS807
can be used to monitor any such out-of-range condition. This
‘OTR’ output is updated along with the data output corre-
sponding to the particular sampled analog input voltage.
Therefore, the OTR data is subject to the same pipeline
delay as the digital data. The OTR output is LOW when the
input voltage is within the defined input range. It will go to
HIGH if the applied signal exceeds the full-scale range.
Data Outputs
The output data format of the ADS807 is in positive Straight
Offset Binary code, as shown in Table II and Table III. This
format can easily be converted into the Binary Two’s Comple-
ment code by inverting the MSB.
It is recommended that the capacitive loading on the data
lines be as low as possible (< 15pF). Higher capacitive
SINGLE-ENDED INPUT
(IN = CM, Pin-23)
+FS – 1LSB (IN = CMV + FSR/2)
+1/2 FS
Bipolar Zero (IN = V_CM)
–1/2 FS
–FS (IN = CMV – FSR/2)
STRAIGHT OFFSET BINARY
(SOB)
1111 1111 1111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0000
TABLE II. Coding Table for Single-Ended Input Configuration
with IN Tied to the Common-Mode Voltage.
DIFFERENTIAL INPUT
+FS – 1LSB (IN = +3V, IN = +2V)
+1/2 FS
Bipolar Zero (IN = IN = V_CM)
–1/2 FS
–FS (IN = +2V, IN = +3V)
STRAIGHT OFFSET BINARY
(SOB)
1111 1111 1111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0000
TABLE III. Coding Table for Single-Ended Input Configuration
with IN Tied to the Common-Mode Voltage.
loading will cause larger dynamic currents as the digital
outputs are changing. Those high current surges can feed
back to the analog portion of the ADS807 and affect the
performance. If necessary, external buffers or latches close
to the converter’s output pins may be used to minimize the
capacitive loading. They also provide the added benefit of
isolating the ADS807 from high-frequency digital noise on
the bus coupling back into the converter.
Digital Output Driver Supply (VDRV)
The ADS807 features a dedicated supply pin for the output
logic drivers, VDRV, which is not internally connected to the
other supply pins. Setting the voltage at VDRV to +5V or
+3V, the ADS807 produces corresponding logic levels and
can directly interface to the selected logic family. The output
stages are designed to supply sufficient current to drive a
variety of logic families. However, it is recommended to use
the ADS807 with +3V logic supply. This will lower the power
dissipation in the output stages due to the lower output swing
and reduce current glitches on the supply line which may
affect the AC performance of the converter. In some applica-
tions, it might be advantageous to decouple the VDRV pin
with additional capacitors or a pi-filter.
GROUNDING AND DECOUPLING
Proper grounding, bypassing, short trace lengths, and the
use of power and ground planes are particularly important for
high-frequency designs. Multilayer PC boards are recom-
mended for best performance since they offer distinct advan-
tages such as minimizing ground impedance, separation of
signal layers by ground layers, etc. The ADS807 should be
treated as an analog component. Whenever possible, the
supply pins should be powered by the analog supply. This
will ensure the most consistent results, since digital supply
lines often carry high levels of noise which otherwise would
be coupled into the converter and degrade the achievable
14
ADS807
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