ADS774H_13 Datasheet, PDF (14/27 Pages) Texas Instruments – Microprocessor-Compatible Sampling CMOS ANALOG-TO-DIGITAL CONVERTER

ADS774H
SBAS443 – AUGUST 2009 ................................................................................................................................................................................................ www.ti.com
STAND-ALONE OPERATION
For stand-alone operation, control of the converter is
accomplished by a single control line connected to
R/C. In this mode, CS and A₀ are connected to digital
common, and CE and 12/8 are connected to +5V.
The output data are presented as 12-bit words.
Stand-alone mode is used in systems that contain
dedicated input ports which do not require full bus
interface capability.
Conversion is initiated by a high-to-low transition of
R/C. The three-state data output buffers are enabled
when R/C is high and STATUS is low. Thus, there
are two possible modes of operation: data can be
read with either a positive pulse on R/C, or a negative
pulse on STATUS. In either case, the R/C pulse must
remain low for a minimum of 25ns.
Figure 1 illustrates timing with an R/C pulse that goes
low and returns high during the conversion. In this
case, the three-state outputs go to the
high-impedance state in response to the falling edge
of R/C and are enabled for external access of the
data after the conversion completes.
Figure 2 illustrates the timing when a positive R/C
pulse is used. In this mode, the output data from the
previous conversion are enabled during the time R/C
is high. A new conversion starts on the falling edge of
R/C, and the three-state outputs return to the
high-impedance state until the next occurrence of a
high R/C pulse. Timing specifications for stand-alone
operation are listed in the TIming Requirements table
for Stand-Alone Mode.
CONVERSION START
The converter initiates a conversion based on a
transition that occurs on any of three logic inputs (CE,
CS, and R/C) as shown in Table 2. Conversion is
initiated by the last of the three inputs to reach the
required state; therefore, all three inputs may be
dynamically controlled. If necessary, all three inputs
may change state simultaneously; in this case, the
nominal delay time is the same regardless of which
input actually starts the conversion. If it is desired that
a particular input establish the actual start of
conversion, the other two inputs should be stable for
a minimum of 50ns before the transition of the critical
input. Timing relationships for the start of conversion
timing are illustrated in Figure 3. The timing
specifications for timing are listed in the Timing
Requirements tables for Fully-Controlled Operation
Convert Mode and Read Mode.
The STATUS output indicates the current state of the
converter because it is in a high state only during
conversion. During this time the three-state output
buffers remain in a high-impedance state, and
therefore data cannot be read during conversion.
Furthermore, during this period, additional transitions
of the three digital inputs that control conversion are
ignored, so that conversion cannot be prematurely
terminated or restarted. However, if A₀ changes state
after the beginning of the conversion, any additional
start conversion transition will latch the new state of
A₀, and possibly generate an incorrect conversion
length (8 bits as opposed to 12 bits) for that
conversion.
FULLY-CONTROLLED OPERATION
Conversion Length
Conversion length (8-bit or 12-bit) is determined by
the state of the A₀ input, which is latched upon
receipt of a conversion start transition (described in
the next section). If A₀ is latched high, the conversion
continues for eight bits. The full 12-bit conversion
occurs if A₀ is low. If all 12 bits are read following an
8-bit conversion, the four LSBs (DB0–DB3) are low
(logic 0). A₀ is latched because it is also involved in
enabling the output buffers. No other control inputs
are latched.
READING OUTPUT DATA
After conversion is initiated, the output data buffers
remain in a high-impedance state until the following
four logic conditions are simultaneously met: R/C
high, STATUS low, CE high, and CS low. Upon
satisfying these conditions, the data lines are enabled
according to the state of inputs 12/8 and A₀. See
Figure 4 for the timing diagram, and the Timing
Requirements tables for Fully-Controlled Operation
Convert Mode and Read Mode for timing
specifications.
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