ADC12V170 Datasheet, PDF (14/32 Pages) National Semiconductor (TI) – 12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with LVDS Outputs

ADC12V170
SNOSAZ1F – MAY 2007 – REVISED APRIL 2013
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Typical Performance Characteristics, DNL, INL
Unless otherwise specified, the following specifications apply: V_IN = -1dBFS, AGND = DGND = DRGND = 0V, V_A = V_D =
+3.3V, V_DR = +1.8V, Internal V_REF = +1.0V, f_CLK = 170 MHz, V_CM = V_RM, C_L = 5 pF/pin, Single-Ended Clock Mode, Offset
Binary Format. Typical values are for T_A = 25°C^(1)(2)(3)(4)
DNL
INL
Figure 4.
Figure 5.
(1) The inputs are protected as shown below. Input voltage magnitudes above V_A or below GND will not damage this device, provided
current is limited per⁽⁴⁾. However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the
Operating Ratings section.
V_A
I/O
To Internal Circuitry
AGND
(2) To ensure accuracy, it is required that |V_A–V_D| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
(3) With the test condition for V_REF = +1.0V (2V_P-P differential input), the 12-Bit LSB is 488.3 µV.
(4) When the input voltage at any pin exceeds the power supplies (that is, V_IN < AGND, or V_IN > V_A), the current at that pin should be
limited to ±5 mA. The ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of ±5 mA to 10.
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