TMS320TCI100 Datasheet, PDF (131/137 Pages) Texas Instruments – FIXED-PIONT DIGTAL SIGNAL PROCESSOR

TMS320TCI100
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
JTAG TEST-PORT TIMING
SPRS218I − MAY 2003 − REVISED APRIL 2009
timing requirements for JTAG test port (see Figure 63)
NO.
1 tc(TCK)
Cycle time, TCK
3 tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high
4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high
−600
−720
MIN MAX
35
10
9
UNIT
ns
ns
ns
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 63)
NO.
PARAMETER
2 td(TCKL-TDOV) Delay time, TCK low to TDO valid
−600
−720
MIN MAX
0
18
UNIT
ns
TCK
TDO
TDI/TMS/TRST
1
2
2
4
3
Figure 63. JTAG Test-Port Timing
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