LM3S9C97 Datasheet, PDF (1306/1337 Pages) Texas Instruments – ARM and Thumb are registered trademarks

Register Quick Reference
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0
USBTXFUNCADDR2, type R/W, offset 0x090, reset 0x00 (see page 993)
ADDR
USBTXFUNCADDR3, type R/W, offset 0x098, reset 0x00 (see page 993)
ADDR
USBTXFUNCADDR4, type R/W, offset 0x0A0, reset 0x00 (see page 993)
ADDR
USBTXFUNCADDR5, type R/W, offset 0x0A8, reset 0x00 (see page 993)
ADDR
USBTXFUNCADDR6, type R/W, offset 0x0B0, reset 0x00 (see page 993)
ADDR
USBTXFUNCADDR7, type R/W, offset 0x0B8, reset 0x00 (see page 993)
ADDR
USBTXFUNCADDR8, type R/W, offset 0x0C0, reset 0x00 (see page 993)
ADDR
USBTXFUNCADDR9, type R/W, offset 0x0C8, reset 0x00 (see page 993)
ADDR
USBTXFUNCADDR10, type R/W, offset 0x0D0, reset 0x00 (see page 993)
ADDR
USBTXFUNCADDR11, type R/W, offset 0x0D8, reset 0x00 (see page 993)
ADDR
USBTXFUNCADDR12, type R/W, offset 0x0E0, reset 0x00 (see page 993)
ADDR
USBTXFUNCADDR13, type R/W, offset 0x0E8, reset 0x00 (see page 993)
ADDR
USBTXFUNCADDR14, type R/W, offset 0x0F0, reset 0x00 (see page 993)
ADDR
USBTXFUNCADDR15, type R/W, offset 0x0F8, reset 0x00 (see page 993)
ADDR
USBTXHUBADDR0, type R/W, offset 0x082, reset 0x00 (see page 995)
ADDR
USBTXHUBADDR1, type R/W, offset 0x08A, reset 0x00 (see page 995)
ADDR
USBTXHUBADDR2, type R/W, offset 0x092, reset 0x00 (see page 995)
ADDR
USBTXHUBADDR3, type R/W, offset 0x09A, reset 0x00 (see page 995)
ADDR
USBTXHUBADDR4, type R/W, offset 0x0A2, reset 0x00 (see page 995)
ADDR
USBTXHUBADDR5, type R/W, offset 0x0AA, reset 0x00 (see page 995)
ADDR
USBTXHUBADDR6, type R/W, offset 0x0B2, reset 0x00 (see page 995)
ADDR
USBTXHUBADDR7, type R/W, offset 0x0BA, reset 0x00 (see page 995)
ADDR
USBTXHUBADDR8, type R/W, offset 0x0C2, reset 0x00 (see page 995)
ADDR
USBTXHUBADDR9, type R/W, offset 0x0CA, reset 0x00 (see page 995)
ADDR
USBTXHUBADDR10, type R/W, offset 0x0D2, reset 0x00 (see page 995)
ADDR
USBTXHUBADDR11, type R/W, offset 0x0DA, reset 0x00 (see page 995)
ADDR
1306
Texas Instruments-Production Data
January 23, 2012