English
Language : 

TX517 Datasheet, PDF (13/19 Pages) Texas Instruments – Dual Channel, High-Voltage – Multi-Level Output Fully Integrated Ultrasound Transmitter
◁
TX517
www.ti.com
SLOS725A – SEPTEMBER 2011 – REVISED JANUARY 2012
APPLICATION INFORMATION
Description
Power Down (Hi-Z Output)
CW Mode
Non-Latch Mode
Latch Mode
Table 1. Truth Table
EN
PDM
PCLKIN
1
0
x (2)
x
0
x
1
1
x
0
1
0/1
CWINA
0
0/1
0
0
CWINB
0
1/0
0
0
INPxx (1)
1
1
0/1
0/1
INNxx (1)
0
0
0/1
0/1
(1) The logic device driving the inputs of the TX517 should include means to prevent a ’shoot-thru’ fault condition. Any input combination
that would result in an INP-input to be Low (0) and an INN-input to be High (1) at the same time on the same output (OUTA or OUTB)
could result in permanent damage to the TX517. See also disallowed logic state table. Table 3 is provided for an example of how to
properly drive the TX517 data inputs INPxx and INNxx.
(2) X = don’t care state. However, in order to prevent excessive power consumption it is recommended that all unused inputs be tied off to
a logic high or logic low. The logic inputs to the device have no internal tie-off’s.
Table 2. Disallowed Logic States
Description
EN
Disallowed mode 1(1)
x
Disallowed mode 2(1)
x
Disallowed mode 3(2)
x
Disallowed mode 4(2)
x
Disallowed mode 5(2)
x
Disallowed mode 6(2)
x
Disallowed mode 7(3)
0
PDM
x
x
0
0
0
0
x
PCLKIN
x
x
x
x
x
x
0
CWINA
x
x
x
x
x
x
x
CWINB
x
x
x
x
x
x
x
INPxA
0
x
x
x
0
x
x
INNxA
1
x
1
x
x
x
x
INPxB
x
0
x
x
x
0
x
INNxB
x
1
x
1
x
x
x
(1) This logic state causes a ’shoot-thru’ fault condition that could result in permanent damage to the TX517.
(2) This logic state causes a high power consumption condition in the internal logic circuitry of the TX517 and could result in a long term
reliability failure of the TX517.
(3) This disallowed logic state is only valid for DC conditions. i.e. it is not allowed to keep PCLKIN at a low logic state when EN\ is at a low
logic state. This causes a high power consumption condition in the internal logic circuitry of the TX517. However, it is acceptable to drive
EN\ low and drive PCLKIN with a clock waveform under the recommended operating conditions for PCLKIN.
Table 3. Example Input Data Set of a 17-Level Output(1)
Output
Level
8
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
off state
INP0A
0
0
0
0
0
0
1
1
1
0
0
1
0
0
1
0
0
0
INP2A
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
INP1A
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INP1B
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
INP2B
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
INP0B
0
0
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
INN0A
0
0
0
0
0
0
1
1
1
0
0
1
0
0
1
0
0
0
INN2A
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
INN1A
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
INN1B
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
INN2B
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
INN0B
0
0
1
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
(1) The levels listed in this table are active high; the P signals need to be inverted before driving the chip. This note is only applicable to
THIS particular table (“the example input data set of a 17-level output).
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): TX517
Submit Documentation Feedback
13
 ▷