TMS470R1VC334A Datasheet, PDF (13/52 Pages) Texas Instruments – 16/32-BIT RISC ROM MICROCONTROLLER

TMS470R1VC334A
16/32-BIT RISC ROM MICROCONTROLLER
SPNS080A – MARCH 2004 – REVISED MARCH 2006
interrupt priority
The central interrupt manager (CIM) portion of the SYS module manages the interrupt requests from the device
modules (i.e., SPI1 or SPI2, SCI1 or SCI2, and RTI, etc.).
Although the CIM can accept up to 32 interrupt request signals, the VC334A device only uses 21 of those
interrupt request signals. The request channels are maskable so that individual channels can be selectively
disabled. All interrupt requests can be programmed in the CIM to be of either type:
O Fast interrupt request (FIQ)
O Normal interrupt request (IRQ)
The precedences of request channels decrease with ascending channel order in the CIM (0 [highest] and
31 [lowest] priority). For these channel priorities and the associated modules, see Table 4.
MODULES
SPI1
RTI
RTI
RTI
SPI2
GIO
Reserved
HET
Reserved
SCI1/SCI2
SCI1
C2SIa
Reserved
Reserved
SCC
Reserved
MibADC
SCI2
Reserved
Reserved
SCI1
System
Reserved
HET
Reserved
SCC
SCI2
MibADC
Reserved
GIO
MibADC
Reserved
Table 4. Interrupt Priority
INTERRUPT SOURCES
SPI1 end-transfer/overrun
COMP2 interrupt
COMP1 interrupt
TAP interrupt
SPI2 end-transfer/overrun
Interrupt A
Interrupt A
SCI1/SCI2 error interrupt
SCI1 receive interrupt
C2SIa interrupt
Interrupt A
End event conversion
SCI2 receive interrupt
SCI1 transmit interrupt
SW interrupt (SSI)
Interrupt B
Interrupt B
SCI2 transmit interrupt
End Group 1 conversion
Interrupt B
End Group 2 conversion
INTERRUPT LEVEL/CHANNEL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251-1443
13