TLV2371-Q1 Datasheet, PDF (13/25 Pages) Texas Instruments – FAMILY OF 550-μA/Ch 3-MHz RAIL-TO-RAIL INPUT/OUTPUT OPERATIONAL AMPLIFIERS

TLV2371-Q1, TLV2372-Q1, TLV2374-Q1
FAMILY OF 550-μA/Ch 3-MHz RAIL-TO-RAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIERS
SGLS244A − MAY 2004 − REVISED JUNE 2008
APPLICATION INFORMATION
rail-to-rail input operation
The TLV237x input stage consists of two differential transistor pairs, NMOS and PMOS, that operate together
to achieve rail-to-rail input operation. The transition point between these two pairs can be seen in Figure 1
through Figure 3 for a 2.7-V, 5-V, and 15-V supply. As the common-mode input voltage approaches the positive
supply rail, the input pair switches from the PMOS differential pair to the NMOS differential pair. This transition
occurs approximately 1.35 V from the positive rail and results in a change in offset voltage due to different device
characteristics between the NMOS and PMOS pairs. If the input signal to the device is large enough to swing
between both rails, this transition results in a reduction in common-mode rejection ratio (CMRR). If the input
signal does not swing between both rails, it is best to bias the signal in the region where only one input pair is
active. This is the region in Figure 1 through Figure 3 where the offset voltage varies slightly across the input
range and optimal CMRR can be achieved. This has the greatest impact when operating from a 2.7-V supply
voltage.
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s
phase margin, leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than
10 pF, it is recommended that a resistor be placed in series (R_NULL) with the output of the amplifier, as shown
in Figure 28. A minimum value of 20 Ω should work well for most applications.
R_F
Input
R_G
−
+
V_DD/2
R_NULL
Output
C_LOAD
Figure 28. Driving a Capacitive Load
offset voltage
The output offset voltage, (V_OO) is the sum of the input offset voltage (V_IO) and both input bias currents (I_IB) times
the corresponding gains. The schematic and formula in Figure 29 can be used to calculate the output offset
voltage.
R_F
I_IB−
R_G
+
−
V_I
+
V_O
R_S
I_IB+
ǒ ǒ ǓǓ ǒ ǒ ǓǓ VOO + VIO
1)
RF
RG
" IIB₎ RS
1)
RF
RG
" IIB– RF
Figure 29. Output Offset Voltage Model
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