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TLC5618_16 Datasheet, PDF (13/25 Pages) Texas Instruments – PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS | |||
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TLC5618, TLC5618A
PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS
APPLICATION INFORMATION
SLAS156G â JULY 1997 â REVISED APRIL 2001
Table 1. Binary Code Table (0 V to 2 VREFIN Output), Gain = 2
1111
1000
1000
0111
0000
INPUT
1111
:
0000
0000
1111
:
0000
1111
0001
0000
1111
0001
Ç ÇOUTPUT
2
VREFIN
4095
4096
:
Ç Ç 2
VREFIN
2049
4096
Ç Ç + 2
VREFIN
2048
4096
VREFIN
Ç Ç 2
VREFIN
2047
4096
Ç Ç:
2
VREFIN
1
4096
0000
0000
0000
0V
buffer amplifier
The output buffer has a rail-to-rail output with short circuit protection and can drive a 2-k⦠load with a 100-pF
load capacitance. Settling time is a software selectable 12.5 µs or 2.5 µs, typical to within ± 0.5 LSB of final value.
external reference
The reference voltage input is buffered, which makes the DAC input resistance not code dependent. Therefore,
the REFIN input resistance is 10 M⦠and the REFIN input capacitance is typically 5 pF, independent of input
code. The reference voltage determines the DAC full-scale output.
logic interface
The logic inputs function with CMOS logic levels. Most of the standard high-speed CMOS logic families may
be used.
serial clock and update rate
Figure 1 shows the TLC5618 timing. The maximum serial clock rate is:
+ Ç Ç ) Ç Ç + f(SCLK)max
1
tw CH min tw CL min
20 MHz
+ Ç Ç Ç ) Ç ÇÇ ) Ç Ç The digital update rate is limited by the chip-select period, which is:
tp(CS) 16 tw CH tw CL
tsu CS1
This equals an 810-ns or 1.23-MHz update rate. However, the DAC settling time to 12 bits limits the update rate
for full-scale input step transitions.
⢠POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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