THS7314_17 Datasheet, PDF (13/31 Pages) Texas Instruments – 3-Channel SDTV Video Amplifier With 5th-Order Filters and 6-dB Gain

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THS7314
SLOS513A – DECEMBER 2006 – REVISED MARCH 2011
DAC/
Encoder
SDTV
CVBS
S-Video Y’
S-Video C’
480i/576i
Y’P’_BP’_R
G’B’R’
3.3 V
CVBS
R
Y’
R
C’
R
THS 7314
1 ^{CH.1 IN}
2 CH.2 IN
3 CH.3 IN
4 ^VS+
CH.1 OUT ₈
CH.2 OUT ₇
CH.3 OUT ₆
GND 5
0.1 mF
+
330 mF
+
CVBS
75 W ^Out
330 mF _{75 W}
+
Y’
Out
S-Video
0.1 mF
C’
75 W
Out
75 W
75 W
3 V to 5 V ^{22 mF}
Figure 29. Typical SDTV CVBS/Y'/C' Inputs From DC-Coupled Encoder/DAC
With AC-Coupled Line Driving
75 W
INPUT MODE OF OPERATION – DC
The inputs to the THS7314 allows for both ac-coupled and dc-coupled inputs. Many DACs or Video Encoders
can be dc connected to the THS7314. One of the drawbacks to dc coupling is when 0-V is applied to the input.
Although the input of the THS7314 allows for a 0-V input signal with no issues, the output swing of a traditional
amplifier cannot yield a 0-V signal resulting in possible clipping. This is true for any single-supply amplifier due to
the limitations of the output transistors. Both CMOS and bipolar transistors cannot go to 0-V while sinking
current. This trait of a transistor is also the same reason why the highest output voltage is always less than the
power supply voltage when sourcing current.
This output clipping can reduce the sync amplitudes (both horizontal and vertical sync amplitudes) on the video
signal. A problem occurs if the receiver of this video signal uses an AGC loop to account for losses in the
transmission line. Some video AGC circuits derive gain from the horizontal sync amplitude. If clipping occurs on
the sync amplitude, then the AGC circuit can increase the gain too much – resulting in too much luma and/or
chroma amplitude gain correction. This may result in a picture with an overly bright display with too much color
saturation.
Other AGC circuits use the chroma burst amplitude for amplitude control, and a reduction in the sync signals
does not alter the proper gain setting. But, it is good engineering design practice to ensure saturation/clipping
does not take place. Transistors always take a finite amount of time to come out of saturation. This saturation
could possibly result in timing delays or other aberrations on the signals.
To eliminate saturation/clipping problems, the THS7314 has a 145-mV input level shift feature. This feature takes
the input voltage and adds an internal +145-mV shift to the signal. Since the THS7314 also has a gain of 6 dB (2
V/V), the resulting output with a 0-V applied input signal is about 290-mV. The THS7314 rail-to-rail output stage
can create this output level while connected to a typical video load with AC or DC coupling. This ensures that no
saturation / clipping of the sync signals occur. This is a constant shift regardless of the input signal. For example,
if a 1-V input is applied, the output is at 2.29-V.
Because the internal gain is fixed at 6 dB, the gain dictates what the allowable linear input voltage range can be
without clipping concerns. For example, if the power supply is set to 3-V, the maximum output is about 2.9-V
while driving a significant amount of current. Thus, to avoid clipping, the allowable input is ((2.9V / 2) – 0.145V) =
1.305V. This is true for up to the maximum recommended 5-V power supply that allows about a ((4.9V / 2) –
0.145V) = 2.305V input range while avoiding clipping on the output.
The input impedance of the THS7314 in this mode of operation is dictated by the internal 800-kΩ pull-down
resistor. This is shown in Figure 30. Note that the internal voltage shift does not appear at the input pin, only the
output pin.
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