SN65LV1021_08 Datasheet, PDF (13/22 Pages) Texas Instruments – 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER

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REN
PWRDN
TCLK
SYNC1
or
SYNC2
D_O±
TCLK
SYNC1
or
SYNC2
D_O±
TCLK
D_O
SN65LV1021
SN65LV1212
SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005
t_w(SP)
DATA
SYNC Pattern
t_w(SP) Min. Timing Met
SYNC Pattern
Figure 10. SYNC Timing Delays
DATA
D_IN
D_IN0 – D_IN9 SYMBOL N
D_IN0 – D_IN9 SYMBOL N+1
t_d(S)
Timing for TCLK_R/F = High
Start
Stop Start
Bit D₀₀ – D₀₉ SYMBOL N–1 Bit Bit
D₀₀ – D₀₉ SYMBOL N
Stop
Bit
Figure 11. Serializer Delay
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