SN65HVD255 Datasheet, PDF (13/26 Pages) Texas Instruments – CAN Transceiver with Fast Loop Times for Highly Loaded Networks

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THERMAL CHARACTERISTICS
13.0
THERMAL METRIC⁽¹⁾
13.1
13.2
13.3
13.4
13.5
θ_JA
θ_JB
θ_JC(TOP)
Ψ_JT
Ψ_JB
Junction-to-air thermal resistance
Junction-to-board thermal resistance⁽³⁾
Junction-to-case (top) thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
13.6
P_D
13.7
Average power dissipation
13.8
Thermal shutdown temperature
13.9
Thermal shutdown hysteresis
SN65HVD255
SN65HVD256, SN65HVD257
SLLSEA2B – DECEMBER 2011 – REVISED JUNE 2012
TEST CONDITIONS
High-K thermal resistance⁽²⁾
V_CC = 5 V, V_RXD = 5 V, T_J = 27°C, R_L = 60 Ω, S at
0 V, Input to TXD at 250 kHz, 25% duty cycle
square wave, C_{L_RXD} = 15 pF. Typical CAN
operating conditions at 500kbps with 25%
transmission (dominant) rate.
V_CC = 5.5 V, V_RXD = 5.5 V, T_J = 150°C, R_L = 50 Ω,
S at 0 V, Input to TXD at 500 kHz, 50% duty cycle
square wave, C_{L_RXD} = 15 pF. Typical high load
CAN operating conditions at 1mbps with 50%
transmission (dominant) rate and loaded network.
TYP
107.5
48.9
56.7
12.1
48.2
115
268
170
5
UNIT
°C/W
mW
°C
°C
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) he junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-top characterization parameter, Ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, Ψ_JB estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
Copyright © 2011–2012, Texas Instruments Incorporated
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