ONET8501PB_17 Datasheet, PDF (13/32 Pages) Texas Instruments – 11.3-Gbps Rate-Selectable Limiting Amplifier

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ONET8501PB
SLLS910A – JULY 2008 – REVISED JUNE 2016
8.6.3 Register 2 (0x02) Mapping – Preemphasis Adjust
BIT 7
—
BIT 6
—
Table 7. Register 2 (0x02) Mapping – Preemphasis Adjust
BIT 5
—
REGISTER ADDRESS 2 (0X02)
BIT 4
BIT 3
—
PEADJ3
BIT 2
PEADJ2
BIT 1
PEADJ1
BIT 0
PEADJ0
8.6.4 Register 3 (0x03) Mapping – Output Amplitude Adjust
BIT 7
—
Table 8. Register 3 (0x03) Mapping – Output Amplitude Adjust
BIT 6
—
BIT 5
—
REGISTER ADDRESS 3 (0X03)
BIT 4
BIT 3
—
—
BIT 2
—
BIT 1
AMP1
BIT 0
AMP0
8.6.5 Register 4 (0x04) Mapping – Rate Selection Register A
BIT 7
RSASEL
Table 9. Register 4 (0x04) Mapping – Rate Selection Register A
BIT 6
—
BIT 5
—
register address 4 (0x04)
BIT 4
BIT 3
—
RSA3
BIT 2
RSA2
BIT 1
RSA1
BIT 0
RSA0
8.6.6 Register 5 (0x05) Mapping – Rate Selection Register B
BIT 7
RSBSEL
Table 10. Register 5 (0x05) Mapping – Rate Selection Register B
BIT 6
—
BIT 5
—
REGISTER ADDRESS 5 (0X05)
BIT 4
BIT 3
—
RSB3
BIT 2
RSB2
BIT 1
RSB1
BIT 0
RSB0
8.6.7 Register 6 (0x06) Mapping – Rate Selection Register C
BIT 7
RSCSEL
Table 11. Register 6 (0x06) Mapping – Rate Selection Register C
BIT 6
—
BIT 5
—
REGISTER ADDRESS 6 (0X06)
BIT 4
BIT 3
—
RSC3
BIT 2
RSC2
BIT 1
RSC1
BIT 0
RSC0
8.6.8 Register 7 (0x07) Mapping – Rate Selection Register D
BIT 7
RSDSEL
Table 12. Register 7 (0x07) Mapping – Rate Selection Register D
BIT 6
—
BIT 5
—
REGISTER ADDRESS 7 (0X07)
BIT 4
BIT 3
—
RSD3
BIT 2
RSD2
BIT 1
RSD1
BIT 0
RSD0
8.6.9 Register 8 (0x08) Mapping – LOS Assert Level Register A
BIT 7
LOSASEL
Table 13. Register 8 (0x08) Mapping – LOS Assert Level Register A
BIT 6
LOSA6
BIT 5
LOSA5
REGISTER ADDRESS 8 (0X08)
BIT 4
BIT 3
LOSA4
LOSA3
BIT 2
LOSA2
BIT 1
LOSA1
BIT 0
LOSA0
Copyright © 2008–2016, Texas Instruments Incorporated
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