ONET2804TLP Datasheet, PDF (13/29 Pages) Texas Instruments – Low-Power, 28-Gbps, 4-Channel Limiting TIA

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ONET2804TLP
SBAS796 – JULY 2017
Feature Description (continued)
If the DC input current exceeds a certain level then this current is partially cancelled by means of a controlled
current source. This cancellation keeps the transimpedance amplifier stage within sufficient operating limits for
optimum performance.
The automatic gain control circuitry adjusts the voltage gain of the AGC amplifier to ensure limiting behavior of
the complete amplifier.
Finally, this circuit block senses the current through the FILTERx FET and generates a mirrored current that is
proportional to the input signal strength. The mirrored currents are available at the RSSIx outputs and can be
sunk to ground (GND) using an external resistor. For proper operation, ensure that the voltage at the RSSIx pad
does not exceed V_CC – 0.65 V.
7.4 Device Functional Modes
The device has two functional modes of operation: pad control mode and two-wire interface control mode.
7.4.1 Pad Control
The default mode of operation is pad control and the amplitude is recommended to be increased to the
450 mV_PP setting by bonding AMPL (pad 6) to V_CC. If further adjustment is desired as described previously, then
the RATE (pad 7), GAIN (pad 8), and TRSH (pad 41) control pads and can be bonded to either ground (GND) or
V_CC.
7.4.2 Two-Wire Interface Control
To enable two-wire interface, the I2CENA (pad 5) control pad must be bonded to V_CC. In this mode of operation,
pad control is not functional and all control is initiated through the two-wire interface as described in the
Programming section.
7.5 Programming
The ONET2804TLP uses a two-wire serial interface for digital control. For example, the two circuit inputs (SDA
and SCK) are driven by the serial data and serial clock from a microcontroller. Both inputs include 10-kΩ pullup
resistors to V_CC. For driving these inputs, an open-drain output is recommended. The two-wire interface allows
write access to the internal memory map to modify control registers and read access to read out control and
status signals. The ONET2804TLP is a slave device only, which means that the device cannot initiate a
transmission, but always relies on the availability of the SCK signal for the duration of the transmission. The
master device provides the clock signal as well as the START and STOP commands. The device is
recommended to be used on a bus with only one master. The protocol for a data transmission is as follows:
1. START command
2. 7-bit slave address (0001100) followed by an eighth bit that is the data direction bit (R/W). A zero indicates a
write operation and a 1 indicates a read operation.
3. 8-bit register address
4. 8-bit register data word
5. STOP command
Regarding timing, the ONET2804TLP is I²C compatible. Figure 13 illustrates the typical timing and Figure 14
illustrates a complete data transfer. Parameters for Figure 13 are defined in the Timing Requirements table.
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