LP38691-ADJ_14 Datasheet, PDF (13/22 Pages) Texas Instruments – 500mA Low Dropout CMOS Linear Regulators with Adjustable Output Stable with Ceramic Output Capacitors

LP38691-ADJ, LP38693-ADJ
www.ti.com
SNVS324I – JANUARY 2005 – REVISED APRIL 2013
WSON MOUNTING
The NGG0006A (No Pullback) 6-Lead WSON package requires specific mounting techniques which are detailed
in the TI AN-1187 Application Report. Referring to the section PCB Design Recommendations (Page 6), it
should be noted that the pad style which should be used with the WSON package is the NSMD (non-solder mask
defined) type. Additionally, it is recommended the PCB terminal pads to be 0.2 mm longer than the package
pads to create a solder fillet to improve reliability and inspection.
The thermal dissipation of the WSON package is directly related to the printed circuit board construction and the
amount of additional copper area connected to the DAP.
The DAP (exposed pad) on the bottom of the WSON package is connected to the die substrate with a conductive
die attach adhesive. The DAP has no direct electrical (wire) connection to any of the pins. There is a parasitic PN
junction between the die substrate and the device ground. As such, it is strongly recommend that the DAP be
connected directly to the ground at device lead 2 (i.e. GND). Alternately, but not recommended, the DAP may be
left floating (i.e. no electrical connection). The DAP must not be connected to any potential other than ground.
For the LP38691SD-ADJ and LP38693SD-ADJ in the NGG0006A 6-Lead WSON package, the junction-to-case
thermal rating, θ_JC, is 10.4°C/W, where the case is the bottom of the package at the center of the DAP. The
junction-to-ambient thermal performance for the LP38691SD-ADJ and LP38693SD-ADJ in the NGG0006A 6-
Lead WSON package, using the JEDEC JESD51 standards is summarized in the following table:
Board
Type
JEDEC
2-Layer
JESD 51-3
JEDEC
4-Layer
JESD 51-7
Thermal
Vias
None
1
2
4
6
θ_JC
10.4°C/W
10.4°C/W
10.4°C/W
10.4°C/W
10.4°C/W
θ_JA
237°C/W
74°C/W
60°C/W
49°C/W
45°C/W
RFI/EMI SUSCEPTIBILITY
RFI (radio frequency interference) and EMI (electromagnetic interference) can degrade any integrated circuit’s
performance because of the small dimensions of the geometries inside the device. In applications where circuit
sources are present which generate signals with significant high frequency energy content (> 1 MHz), care must
be taken to ensure that this does not affect the IC regulator.
If RFI/EMI noise is present on the input side of the regulator (such as applications where the input source comes
from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the IC.
If a load is connected to the IC output which switches at high speed (such as a clock), the high-frequency current
pulses required by the load must be supplied by the capacitors on the IC output. Since the bandwidth of the
regulator loop is less than 100 kHz, the control circuitry cannot respond to load changes above that frequency.
This means the effective output impedance of the IC at frequencies above 100 kHz is determined only by the
output capacitor(s).
In applications where the load is switching at high speed, the output of the IC may need RF isolation from the
load. It is recommended that some inductance be placed between the output capacitor and the load, and good
RF bypass capacitors be placed directly across the load.
PCB layout is also critical in high noise environments, since RFI/EMI is easily radiated directly into PC traces.
Noisy circuitry should be isolated from "clean" circuits where possible, and grounded through a separate path. At
MHz frequencies, ground planes begin to look inductive and RFI/ EMI can cause ground bounce across the
ground plane. In multi-layer PCB applications, care should be taken in layout so that noisy power and ground
planes do not radiate directly into adjacent layers which carry analog power and ground.
Copyright © 2005–2013, Texas Instruments Incorporated
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